FemtoClock
®
Crystal-to-LVDS
Clock Generator
General Description
The ICS844252-04 is a 10Gb/12Gb Ethernet Clock Generator. The
ICS844252-04 can synthesize 10 Gigabit Ethernet and 12 Gigabit
Ethernet with a 25MHz crystal. It can also generate SATA and 10Gb
Fibre Channel reference clock frequencies with the appropriate
choice of crystals. The ICS844252-04 has excellent phase jitter
performance and is packaged in a small 16-pin TSSOP, making it
ideal for use in systems with limited board space.
ICS844252-04
DATASHEET
Features
•
•
•
•
•
•
•
•
Two differential LVDS output pairs
Crystal input frequency range: 20MHz – 30MHz
Output frequency range: 150MHz – 187.5MHz
VCO range: 600MHz - 750MHz
RMS phase jitter @ 156.25MHz (1.875MHz – 20MHz):
0.31ps (typical)
Full 3.3V supply mode
0°C to 70°C ambient operating temperature
Lead-free (RoHS 6) packaging
Configuration Table with 25MHz Crystal
Inputs
Crystal Frequency
(MHz)
25
25
Feedback Divide
30
25
VCO Frequency
(MHz)
750
625
N Output
Divide
4
4
Output Frequency
(MHz)
187.5
156.25
Application
12 Gigabit Ethernet
10 Gigabit Ethernet
Configuration Table with Selectable Crystals
Inputs
Crystal Frequency
(MHz)
20
21.25
24
25.5
30
Feedback Divide
30
30
25
25
25
VCO Frequency
(MHz)
600
637.5
600
637.5
750
N Output
Divide
4
4
4
4
4
Output Frequency
(MHz)
150
159.375
150
159.375
187.5
Application
SATA
10 Gigabit Ethernet
SATA
10 Gigabit Ethernet
12 Gigabit Ethernet
Block Diagram
OE
nPLL_SEL
REF_CLK
Pullup
Pulldown
Pin Assignment
D
Q
LE
1
nQ1
Q1
V
DDO
OE
nPLL_SEL
V
DDO
Q0
nQ0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTAL_IN
XTAL_OUT
GND
REF_CLK
CLK_SEL
V
DD
V
DDA
FREQ_SEL
Pulldown
1
XTAL_IN
OSC
XTAL_OUT
CLK_SEL
Pulldown
0
Phase
Detector
VCO
600MHz-750MHz
DIV. N
÷4
0
Q0
nQ0
Q1
nQ1
ICS844252-04
16-Lead TSSOP
4.4mm x 5mm x 0.925mm
package body
G Package
Top View
0 = ÷25
(default)
1 = ÷30
FREQ_SEL
Pulldown
ICS844252AG-04 REVISION A JANUARY 20, 2014
1
©2014 Integrated Device Technology, Inc.
ICS844252-04 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS CLOCK GENERATOR
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1, 2
3, 6
4
Name
nQ1, Q1
V
DDO
OE
Output
Power
Input
Pullup
Type
Description
Differential output pair. LVDS interface levels.
Output supply pins.
Output enable. When HIGH, clock outputs follow clock input. When LOW,
Qx outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL
interface levels.
When Low, selects PLL. When High, bypasses the PLL. LVCMOS/LVTTL
interface levels.
Differential output pair. LVDS interface levels.
Pulldown
Frequency select pin. LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Pulldown
Pulldown
Clock select input. When Low, selects crystal inputs. When High, selects
REF_CLK. LVCMOS/LVTTL interface levels.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
5
7, 8
9
10
11
12
13
14
15,
16
nPLL_SEL
Q0, nQ0
FREQ_SEL
V
DDA
V
DD
CLK_SEL
REF_CLK
GND
XTAL_OUT,
XTAL_IN
Input
Output
Input
Power
Power
Input
Input
Power
Input
Pulldown
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
REF_CLK, OE, nPLL_SEL,
CLK_SEL, FREQ_SEL
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
ICS844252AG-04 REVISION A JANUARY 20, 2014
2
©2014 Integrated Device Technology, Inc.
ICS844252-04 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
0V to V
DD
10mA
15mA
92.4C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Positive Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.16
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
84
16
52
Units
V
V
V
mA
mA
mA
Table 3B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
nPLL_SEL,
REF_CLK
FREQ_SEL,
CLK_SEL
OE
nPLL_SEL,
REF_CLK
FREQ_SEL,
CLK_SEL
OE
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
Units
V
V
I
IH
Input
High Current
V
DD
= V
IN
= 3.465V
150
µA
V
DD
= V
IN
= 3.465V
5
µA
I
IL
Input
Low Current
V
DD
= 3.465V, V
IN
= 0V
-5
µA
V
DD
= 3.465V, V
IN
= 0V
-150
µA
ICS844252AG-04 REVISION A JANUARY 20, 2014
3
©2014 Integrated Device Technology, Inc.
ICS844252-04 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS CLOCK GENERATOR
Table 3C. LVDS DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.125
Test Conditions
Minimum
247
Typical
Maximum
485
50
1.45
50
Units
mV
mV
V
mV
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Capacitive Loading (CL)
12
20
Test Conditions
Minimum
Typical
Fundamental
30
50
7
18
MHz
pF
pF
Maximum
Units
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
f
OUT
tsk(o)
Parameter
Output Frequency Range
Output Skew; NOTE 1, 2
156.25MHz (1.875MHz – 20MHz)
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
Output Duty Cycle
159.375MHz (1.875MHz –
20MHz):
187.5MHz (1.875MHz – 20MHz)
t
R
/ t
F
odc
20% to 80%
nPLL_SEL = 0
300
48
0.31
0.31
0.33
500
52
Test Conditions
Minimum
150
Typical
Maximum
187.5
15
Units
MHz
ps
ps
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized using a crystal with CL = 18pF.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Refer to the Phase Noise Plots.
ICS844252AG-04 REVISION A JANUARY 20, 2014
4
©2014 Integrated Device Technology, Inc.
ICS844252-04 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS CLOCK GENERATOR
Typical Phase Noise at 156.25MHz
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.31ps (typical)
Noise Power (dBc/Hz)
Offset Frequency (Hz)
ICS844252AG-04 REVISION A JANUARY 20, 2014
5
©2014 Integrated Device Technology, Inc.
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