CY7C1061G30-10ZSXIES datasheet, PDF

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CY7C1061G30-10ZSXIES: DescriptionSRAM 16Mb 2.2V-3.6V 10ns Asyn SRAM with ECC; Categorystorage; File Size552KB，25 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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CY7C1061G30-10ZSXIES Overview

SRAM 16Mb 2.2V-3.6V 10ns Asyn SRAM with ECC

CY7C1061G30-10ZSXIES Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Cypress Semiconductor
Product Category	SRAM
RoHS	Details
Memory Size	16 Mbit
Organization	1 M x 16
Access Time	10 ns
Interface Type	Parallel
Supply Voltage - Max	3.6 V
Supply Voltage - Min	2.2 V
Supply Current - Max	110 mA
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	VFBGA-48
Packaging	Tray
Memory Type	SDR
Type	Asynchronous
Factory Pack Quantity	108
Unit Weight	0.007873 oz

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CY7C1061G/CY7C1061GE

16-Mbit (1M words × 16 bit) Static RAM

with Error-Correcting Code (ECC)

16-Mbit (1M words × 16 bit) Static RAM with Error-Correcting Code (ECC)

Features

■

High speed

❐

= 10 ns/15 ns

Embedded error-correcting code (ECC) for single-bit error

correction

Low active and standby currents

❐

= 90 mA typical at 100 MHz

❐

SB2

= 20 mA typical

Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and

4.5 V to 5.5 V

1.0 V data retention

Transistor-transistor logic (TTL) compatible inputs and outputs

Error indication (ERR) pin to indicate 1-bit error detection and

correction

Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball

VFBGA packages

To access devices with a single chip enable input, assert the chip

enable (CE) input LOW. To access dual chip enable devices,

assert both chip enable inputs – CE

as LOW and CE

as HIGH.

To perform data writes, assert the Write Enable (WE) input LOW,

and provide the data and address on the device data pins (I/O

through I/O

) and address pins (A

through A

) respectively.

The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs

control byte writes, and write data on the corresponding I/O lines

to the memory location specified. BHE controls I/O

through

I/O

and BLE controls I/O

through I/O

To perform data reads, assert the Output Enable (OE) input and

provide the required address on the address lines. Read data is

accessible on I/O lines (I/O

through I/O

). You can perform

byte accesses by asserting the required byte enable signal (BHE

or BLE) to read either the upper byte or the lower byte of data

from the specified address location.

All I/Os (I/O

through I/O

) are placed in a high-impedance state

when the device is deselected (CE HIGH for a single chip enable

device and CE

HIGH / CE

LOW for a dual chip enable device),

or control signals are de-asserted (OE, BLE, BHE).

On the CY7C1061GE devices, the detection and correction of a

single-bit error in the accessed location is indicated by the

assertion of the ERR output (ERR = High). See the

Truth Table

on page 16

for a complete description of read and write modes.

The logic block diagrams are on page 2.

The CY7C1061G and CY7C1061GE devices are available in

48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages.

For a complete list of related documentation, click

here.

■

Functional Description

CY7C1061G and CY7C1061GE are high-performance CMOS

fast static RAM devices with embedded ECC

[1]

. Both devices are

offered in single and dual chip enable options and in multiple pin

configurations. The CY7C1061GE device includes an ERR pin

that signals a single-bit error-detection and correction event

during a read cycle.

Product Portfolio

Current Consumption

Product

Features and Options

(see

Pin Configurations on

page 4)

Single or dual chip enables

Optional ERR pins

Address MSB A

placement options

compatible with Cypress and

other vendors

Range

(V)

1.65 V–2.2 V

2.2 V–3.6 V

4.5 V–5.5 V

Speed Operating I

, (mA)

(ns)

f = f

max

10/15

Typ

[2]

Max

110

Standby, I

SB2

(mA)

Typ

[2]

Max

CY7C1061G18

CY7C1061G(E)30

CY7C1061G

Industrial

Notes

1. This device does not support automatic write-back on error detection.

2. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V

= 1.8 V (for a V

range of 1.65 V–2.2 V),

= 3 V (for a V

range of 2.2 V–3.6 V), and V

= 5 V (for a V

range of 4.5 V–5.5 V), T

= 25 °C.

Cypress Semiconductor Corporation

Document Number: 001-81540 Rev. *S

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised June 16, 2017

CY7C1061G30-10ZSXIES Related Products

	CY7C1061G30-10ZSXIES	CY7C1061G18-15BV1XIES	CY7C1061G18-15ZXI	CY7C1061G18-15ZSXI	CY7C1061GE30-10BVXIES	CY7C1061GE-10ZSXI	CY7C1061G30-10ZXET	CY7C1061G18-15ZSXIT	CY7C1061G30-10BV1XET
Description	SRAM 16Mb 2.2V-3.6V 10ns Asyn SRAM with ECC	SRAM 16Mb 1.65V-2.2V 15ns Asyn SRAM with ECC	SRAM Async SRAMS	SRAM Async SRAMS	SRAM 16Mb 2.2V-3.6V 10ns Asyn SRAM with ECC	SRAM Async SRAMS	SRAM ASYNC SRAMS	SRAM Async SRAMS	SRAM Async SRAMS
Product Attribute	Attribute Value	Attribute Value	Attribute Value	-	Attribute Value	Attribute Value	Attribute Value	Attribute Value	Attribute Value
Manufacturer	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	-	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
Product Category	SRAM	SRAM	SRAM	-	SRAM	SRAM	SRAM	SRAM	SRAM
RoHS	Details	Details	Details	-	Details	Details	Details	Details	Details
Packaging	Tray	Tray	Tray	-	Tray	Tray	Reel	Reel	Reel
Factory Pack Quantity	108	480	96	-	480	108	1000	1000	2000
Moisture Sensitive	-	-	Yes	-	-	Yes	Yes	Yes	Yes

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