Low Skew, 1-to-16 Differential-to-3.3V
LVPECL Fanout Buffer
8530I-01
Datasheet
General Description
The 8530I-01is a low skew, 1-to-16 Differential- to-3.3V LVPECL
Fanout Buffer. The CLK, nCLK pair can accept most standard
differential input levels. The high gain differential amplifier accepts
peak-to-peak input voltages as small as 150mV as long as the
common mode voltage is within the specified minimum and
maximum range.
Guaranteed output and part-to-part skew characteristics make the
8530I-01 ideal for those clock distribution applications demanding
well defined performance and repeatability.
Features
•
•
•
•
•
•
•
•
•
•
Sixteen differential 3.3V LVPECL output pairs
CLK, nCLK input pair
CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V LVPECL levels
with a resistor bias on nCLK input
Output skew: 75ps (maximum)
Additive phase jitter, RMS @ 106.25MHz: 0.162ps (typical)
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK0
Pulldown
nCLK0
Pullup
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
Pin Assignment
Q12
nQ13
Q13
V
EE
nQ14
Q14
V
CCO
nQ12
nCLK
nQ15
Q15
V
CCO
V
CCO
Q11
nQ11
Q10
nQ10
V
EE
Q9
nQ9
Q8
nQ8
V
CCO
V
CC
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
5
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
V
CC
V
CCO
Q7
nQ7
Q6
nQ6
V
EE
Q5
nQ5
Q4
nQ4
V
CCO
CLK
V
CCO
nQ0
Q0
nQ1
Q1
V
EE
nQ2
Q2
nQ3
Q3
V
CCO
8530I-01
48-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm package body
Y Package
Top View
©2015 Integrated Device Technology, Inc.
1
Revision B, December 1, 2015
8530I-01 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 11, 14, 24, 25, 35, 38, 48
2, 3
4, 5
6, 19, 30, 43
7, 8
9, 10
12, 13
15, 16
17, 18
20, 21
22, 23
26, 27
28, 29
31, 32
33, 34
36
37
39, 40
41. 42
44, 45
46, 47
Name
V
CCO
Q11, nQ11
Q10, nQ10
V
EE
Q9, nQ9
Q8, nQ8
V
CC
Q7, nQ7
Q6, nQ6
Q5, nQ5
Q4, nQ4
Q3, nQ3
Q2, nQ2
Q1, nQ1
Q0, nQ0
CLK
nCLK
Q15, nQ15
Q14, nQ14
Q13, nQ13
Q12, nQ12
Power
Output
Output
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Output
Output
Pulldown
Pullup
Type
Description
Output power supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative power supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Positive power supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
©2015 Integrated Device Technology, Inc.
2
Revision B, December 1, 2015
8530I-01 Datasheet
Function Table
Table 3. Clock Input Function Table
Inputs
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
Q[0:15]
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQ[0:15]
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Refer to the Application Information section,
Wiring the Differential Input to Accept single-ended Levels.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
34.1°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CCO
I
EE
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
150
Units
V
V
mA
©2015 Integrated Device Technology, Inc.
3
Revision B, December 1, 2015
8530I-01 Datasheet
Table 4B. Differential Input DC Characteristics, V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input High Current
5
-5
I
IL
V
PP
V
CMR
Input Low Current
-150
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
0.15
V
EE
+ 0.5
1.3
V
CC
– 0.85
µA
V
V
µA
µA
Test Conditions
Minimum
Typical
Maximum
150
Units
µA
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH.
Table 4C. LVPECL DC Characteristics, V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
– 1.4
V
CCO
– 2.0
0.6
Typical
Maximum
V
CCO
– 0.9
V
CCO
– 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50 to V
CCO
– 2V.
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
OUT
Parameter
Output Frequency
Test Conditions
106.25MHz,
Integration Range: 12kHz – 20MHz
212.5MHz,
Integration Range: 12kHz – 20MHz
Minimum
Typical
Maximum
500
Units
MHz
ps
ps
t
JIT
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 2, 4
Output Duty Cycle
Output Rise/ Fall Time
0.162
0.152
1
2
75
700
47
53
700
t
PD
tsk(o)
tsk(pp)
odc
t
R
/ t
F
ns
ps
ps
%
ps
20% to 80%
300
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
©2015 Integrated Device Technology, Inc.
4
Revision B, December 1, 2015
8530I-01 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase
noise is defined as the ratio of the noise power present in a 1Hz band
at a specified offset from the fundamental frequency to the power
value of the fundamental. This ratio is expressed in decibels (dBm)
or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a
dBc
value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 106.25MHz
12kHz to 20MHz = 0.162ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
©2015 Integrated Device Technology, Inc.
5
Revision B, December 1, 2015
京公网安备 11010802033920号
EEWORLD
