Clock Generator for Cavium Processors
ICS8430S10I
DATA SHEET
General Description
The ICS8430S10I is a PLL-based clock generator specifically
designed for Cavium Networks SoC processors. This high
performance device is optimized to generate the processor core
reference clock, the DDR reference clocks, the PCI/PCI-X bus
clocks, and the clocks for both the Gigabit Ethernet MAC and PHY.
The clock generator offers ultra low-jitter, low-skew clock outputs,
and edge rates that easily meet the input requirements for the
CN30XX/ CN31XX/CN38XX/CN58XX processors. The output
frequencies are generated from a 25MHz external input source or an
external 25MHz parallel resonant crystal. The extended temperature
range of the ICS8430S10I supports telecommunication, networking,
and storage requirements.
Features
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One selectable clock for DDR 400/533/667, LVPECL/LVDS
interface levels
Nine LVCMOS/ LVTTL outputs, 15Ω typical output impedance
Selectable external crystal or differential input source
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, SSTL
input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Power output supply modes
LVDS and LVPECL – full 3.3V
LVCMOS – full 3.3V or mixed 3.3V core/2.5V output
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Applications
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Systems using Cavium Processors
CPE Gateway Design
Home Media Servers
802.11n AP or Gateway
SOHO Secure Gateway
SOHO SME Gateway
V
DDO_REF
nOE_E
GND
QREF0
QREF1
Pin Assignment
QREF2
LVDS_SEL
GND
QE
V
DDO_E
V
DDO_CD
QC
QD0
QD1
CORE_SEL
GND
GND
MR/ nOE_REF
V
DDO_B
QB0
QB1
V
DDO_B
GND
V
DDO_REF
Wireless Soho and SME VPN Solutions
Wired and Wireless Network Security
Web Servers and Exchange Servers
V
DD
nOE_D
GND
nPLL_SEL
XTAL_IN
XTAL_OUT
nXTAL_SEL
CLK
nCLK
nOE_C
nOE_B
GND
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
ICS8430S10I
33
48-Pin TQFP, E-Pad
32
5
7mm x 7mm x 1mm
6
31
7
30
package body
8
29
Y Package
9
28
Top View
10
27
26
11
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
nOE_A
SPI_SEL1
DDR_SEL1
DDR_SEL0
nQA
SPI_SEL0
PCI_SEL1
PCI_SEL0
QA
V
DD
V
DDA
V
DD
ICS8430S10AYI REVISION B JANUARY 14, 2011
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©2011 Integrated Device Technology, Inc.
ICS8430S10I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Block Diagram
ICS8430S10AYI REVISION B JANUARY 14, 2011
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©2011 Integrated Device Technology, Inc.
ICS8430S10I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Table 1. Pin Descriptions
Number
1, 13, 23
2
3, 12, 30, 31,
39, 42, 46
4
5,
6
7
8
9
Name
V
DD
nOE_D
Power
Input
Pulldown
Type
Description
Core supply pins.
Active LOW output enable for Bank D outputs. When logic HIGH, the outputs are
in high impedance (HI-Z). When logic LOW, the outputs are enabled.
LVCMOS/LVTTL interface levels.
Power supply ground.
Pulldown
PLL bypass. When LOW, selects PLL (PLL Enable). When HIGH, deselects the
reference clock (PLL Bypass). LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Selects XTAL inputs when LOW. Selects differential clock (CLK, nCLK) input
when HIGH. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V
DD
/2.
Active LOW output enable for Bank C output. When logic HIGH, QC output is in
high impedance (HI-Z). When logic LOW, QC output is enabled. LVCMOS/LVTTL
interface levels.
Active LOW output enable for Bank B outputs. When logic HIGH, the outputs are
in high impedance (HI-Z). When logic LOW, the outputs are enabled.
LVCMOS/LVTTL interface levels.
Active LOW output enable for Bank A outputs. When logic HIGH, the output pair
drives differential LOW (QA = LOW, nQA = HIGH). When logic LOW, the outputs
are enabled. LVCMOS/LVTTL interface levels.
Selects the SPI PLL reference clock output frequency. See Table 3D.
Selects the PC,I PCI-X reference clock output frequency. See Table 3C.
LVCMOS/LVTTL interface levels.
Selects the DDR reference clock output frequency. See Table 3B.
LVCMOS/LVTTL interface levels.
Differential output pair. Selectable between LVPECL and LVDS interface levels.
Analog supply pin.
Bank B output supply pins. 3.3 V or 2.5V supply.
Single-ended Bank B outputs. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the QREF[2:0] outputs are in high impedance
(HI-Z). When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/ LVTTL interface levels.
Selects the processor core clock output frequency. The output frequency is
50MHz when LOW, and 33.333MHz when HIGH. See Table 3A. LVCMOS/LVTTL
interface levels.
Single-end Bank D outputs. LVCMOS/LVTTL interface levels.
Single-end Bank C output. LVCMOS/LVTTL interface levels.
Bank C and Bank D output supply pin. 3.3 V or 2.5V supply.
GND
nPLL_SEL
XTAL_IN,
XTAL_OUT
nXTAL_SEL
CLK
nCLK
Power
Input
Input
Input
Input
Input
10
nOE_C
Input
11
nOE_B
Input
Pulldown
14
15,
16
17,
18
19,
20
21, 22
24
25, 28
26, 27
nOE_A
SPI_SEL1,
SPI_SEL0
PCI_SEL1,
PCI_SEL0
DDR_SEL1,
DDR_SEL0
nQA, QA
V
DDA
V
DDO_B
QB1, QB0
Input
Pulldown
Input
Input
Input
Output
Power
Power
Output
Pulldown
Pulldown
Pulldown
29
MR/nOE_REF
Input
Pulldown
32
33, 34
35
36
CORE_SEL
QD1, QD0
QC
V
DDO_CD
Input
Output
Output
Power
Pulldown
Pin descriptions continue on the next page.
ICS8430S10AYI REVISION B JANUARY 14, 2011
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©2011 Integrated Device Technology, Inc.
ICS8430S10I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Number
37
38
40
41, 48
43,
44,
45
47
Name
V
DDO_E
QE
LVDS_SEL
V
DDO_REF
QREF2,
QREF1,
QREF0
nOE_E
Power
Output
Input
Power
Output
Type
Description
Bank E output supply pin. 3.3 V or 2.5V supply.
Single-end Bank E output. LVCMOS/LVTTL interface levels.
Pulldown
Selects between LVDS and LVPECL interface levels on differential output pair QA
and nQA. When LOW, LVDS interface levels are selected. When HIGH, LVPECL
is selected. See table 3E.
Bank QREF output supply pins. 3.3 V or 2.5V supply.
Single-ended reference clock outputs. LVCMOS/LVTTL interface levels.
Active LOW output enable for Bank E outputs. When logic HIGH, the outputs are
in high impedance (HI-Z). When logic LOW, the outputs are enabled.
LVCMOS/LVTTL interface levels.
Input
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
V
DD,
V
DDO_X
= 3.465V
V
DD
= 3.465V, V
DDO_X
= 2.625V
Test Conditions
Minimum
Typical
2
4
4
51
51
V
DDO_X
= 3.465V
15
Maximum
Units
pF
pF
pF
k
Ω
k
Ω
R
PULLDOWN
Input Pulldown Resistor
QB[0:1], QC,
QD[0:1], QE
QREF[0:2]
QB[0:1], QC,
QD[0:1], QE
QREF[0:2]
Ω
R
OUT
Output Impedance
V
DDO_X
= 2.625V
20
Ω
NOTE: V
DDO_X
denotes V
DDO_B
, V
DDO_CD
, V
DDO_E
and V
DDO_REF.
ICS8430S10AYI REVISION B JANUARY 14, 2011
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©2011 Integrated Device Technology, Inc.
ICS8430S10I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Function Tables
Table 3A. CORE_SEL Control Input Function Table
Input
CORE_SEL
0 (default)
1
Output Frequency
QB[0:1]
50MHz
33.333MHz
Table 3B. DDR_SEL Control Input Function Table
Inputs
DDR_SEL1
0 (default)
0
1
1
DDR_SEL0
0 (default)
1
0
1
Output Frequency
QA, nQA
133.333MHz
100.000MHz
83.333MHz
125.000MHz
Table 3C. PCI_SEL Control Input Function Table
Inputs
PCI_SEL1
0 (default)
0
1
1
PCI_SEL0
0 (default)
1
0
1
Output Frequency
QC
133.333MHz
100.000MHz
66.6667MHz
33.333MHz
Table 3D. SPI_SEL Control Input Function Table
Inputs
SPI_SEL1
0 (default)
0
1
SPI_SEL0
0 (default)
1
0
Output Frequency
QD[0:1]
100.000MHz
125.000MHz
80.000MHz
Table 3E. LVDS_SEL Control Input Function Table
Input
LVDS_SEL
0 (default)
1
Output Levels
QA, nQA
LVDS
LVPECL
ICS8430S10AYI REVISION B JANUARY 14, 2011
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©2011 Integrated Device Technology, Inc.
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