CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
SUPPLY
I
S
I
SD
ANALOG
V
OL
V
OH
I
SC
PSRR
t
D
V
AC
ΔV
MIS
V
DROOP
R
INH
REG
CAP
DIGITAL
V
IH
Supply Current
V
S
= 15V, V
SD
= 5V, V
REFH
= 13V, V
REFL
= 2V, R
L
= 1.5kΩ and C
L
= 200pF to 0V, T
A
= 25°C, unless
otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
No load
10.2
0.17
12.5
0.35
mA
mA
Digital Supply Current
Output Swing Low
Output Swing High
Short Circuit Current
Power Supply Rejection Ratio
Program to Out Delay
Accuracy referred to the ideal value
Channel to Channel Mismatch
Droop Voltage
Input Resistance @ V
REFH
, V
REFL
Load Regulation
Band Gap
Sinking 5mA (V
REFH
= 15V, V
REFL
= 0)
Sourcing 5mA (V
REFH
= 15V, V
REFL
= 0)
R
L
= 10Ω
V
S
+ is moved from 14V to 16V
14.85
100
45
50
14.95
140
65
4
150
mV
V
mA
dB
ms
mV
mV
Code = 512
Code = 512
20
2
1
32
2
mV/ms
kΩ
I
OUT
= 5mA step
By pass with 0.1µF
1
0.5
1.3
1.5
1.6
mV/mA
V
Logic 1 Input Voltage
V
SD
= 5V
V
SD
= 3.3V
4
2
5
V
V
MHz
V
ns
ns
ns
ns
ns
GΩ
µs
%
LSB
LSB
kHz
V
100
µA
F
CLK
V
IL
t
S
t
H
t
LC
t
CE
t
DCO
R
SDIN
T
PULSE
Duty Cycle
INL
DNL
F_OSC
V
IH_SHDN
I
IH_SHDN
Clock Frequency
Logic 0 Input Voltage
Setup Time
Hold Time
Load to Clock Time
Clock to Load Line
Clock to Out Delay Time
S
DIN
Input Resistance
Minimum Pulse Width for EXT_OSC Signal
Duty Cycle for EXT_OSC Signal
Integral Nonlinearity Error
Differential Nonlinearity Error
Internal Refresh Oscillator Frequency
SHDN Voltage Input High
SHDN Current Input High
SHDN = 2V
OSC_Select = 0
2
Negative edge of SCLK
V
SD
= 3.3V/5V
20
20
20
20
10
1
5
50
1.3
0.5
21
1
2
EL5325A
Pin Descriptions
EL5325A
1
2
3
4
5
6, 11
7
8
9
10
12
13
14
17
19
20
21
22
23
24
26
27
28
15
16
18, 25
PIN NAME
ENA
SDI
SCLK
SDO
EXT_OSC
VS+
SHDN
VSD
REFH
REFL
GND
CAP
NC
OUTJ
OUTI
OUTH
OUTG
OUTF
OUTE
OUTD
OUTC
OUTB
OUTA
OUTL
OUTK
GND
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Power
PIN TYPE
Logic Input
Logic Input
Logic Input
Logic Output
Logic Input/Output
Analog Power
Logic Input
Digital Power
Analog Reference Input
Analog Reference Input
Ground
Analog Bypass Pin
PIN FUNCTION
Chip select, low enables data input to logic
Serial data input
Serial data clock
Serial data output
External oscillator input or internal oscillator output
Positive supply voltage for analog circuits
Chip shutdown: float enables chip, high > 2V disables chip
Positive power supply for digital circuits (3.3V - 5V)
High reference voltage
Low reference voltage
Ground
Decoupling capacitor for internal reference generator, 0.1µF
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