FAN1655 3A DDR Bus Termination Regulator
January 2006
FAN1655
3A DDR Bus Termination Regulator
Description
The FAN1655 is a low-cost bi-directional LDO
specifically designed for terminating DDR memory bus. It
can both sink and source up to 2.1A continuous, 3A
peak, providing enough current for most DDR appli-
cations. Load regulation meets the JEDEC spec, VTT =
VREFOUT ± 40mV.
The FAN1655 includes a buffered reference voltage
capable of supplying up to 5mA current. On-chip thermal
limiting provides protection against a combination of
power overload and ambient temperature that would
create an excessive junction temperature. A shutdown
input puts the FAN1655 into a low power mode.
The FAN1655 regulator is available in a power-enhanced
eTSSOP™-16, standard SOIC-14, and an 8-Lead MLP
package.
Features
■
Sinks and sources 2.1A continuous, 3A peak
■
0 to +125°C operating temperature range
■
5mA Buffered VREFOUT = VDDQ/2
■
Load regulation: VTT = VREFOUT ± 40mV
■
On-chip thermal limiting
■
Low Cost SO-14, Power-Enhanced eTSSOP or
8-pin 5x6mm MLP packages
■
Low-Current Shutdown Mode
■
Output Short Circuit Protection
Applications
■
DDR Terminator VTT supply
Ordering Information
Part Number
FAN1655M
FAN1655MX
FAN1655MTF
FAN1655MTFX
FAN1655MPX
Temperature Range
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
Package
SOIC-14
SOIC-14
eTSSOP-16
eTSSOP-16
MLP-8
Packing
Rails
Tape and Reel
Rails
Tape and Reel
Tape and Reel
Block Diagram
VDDQ
200k
–
VREFOUT
VREFIN
+
VTTFORCE
+
VTTFORCE
–
200k
VTTSENSE
FAN1655
VSSQ
VSS
VSS
VSS
VDD
VDD
VDD
SHDN
©2006 Fairchild Semiconductor Corporation
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FAN1655 Rev. 1.1.5
FAN1655 3A DDR Bus Termination Regulator
Pin Assignments
VDD
VDD
VTTFORCE
VSS
VSS
VTTFORCE
VDD
VSS
1
2
3
4
5
6
7
8
FAN1655
16
15
14
13
12
11
10
9
NC
VDDQ
VREFOUT
VSSQ
SHDN
VREFIN
VTTSENSE
NC
VDD
VDD
VTTFORCE
VSS
VSS
VTTFORCE
VDD
1
2
3
4
5
6
7
FAN1655M
14
13
12
11
10
9
8
VDDQ
VREFOUT
VSSQ
SHDN
VREFIN
VTTSENSE
VSS
16-Lead Plastic eTSSOP-16
θ
JC
= 4˚C/W*
*Thermal impedance is measured with the power
pad soldered to a 0.5 square inch copper area.
The copper area should be connected to Vss
(ground) and positioned over an internal power
or ground plane to assist in heat dissipation.
14-Lead Plastic SOIC
θ
JC
= 37˚C/W,
θ
JA
= 88˚C/W
VDD
VTTFORCE
VTTFORCE
VDD
1
2
3
4
8
7
6
5
VDDQ
VREFOUT
SHDN
VTTSENSE
GND
8-Lead MLP Package (5x6mm)
θ
JC
= 4˚C/W,
θ
JA
= 34˚C/W
as measured on FAN1655MP Eval Board
Pin Definitions
Pin
MLP
1, 4
2, 3
PAD
5
eTSSOP
1, 2, 7
3, 6
4, 5, 8
10
11
SOIC-14
1, 2, 7
3, 6
4, 5, 8
9
10
11
Pin Name
VDD
VTTFORCE
VSS
VTTSENSE
VREFIN
SHDN
Pin Function
Input power for the LDO.
The VTT output voltage.
IC Ground.
Feedback for remote sense of the VTT voltage.
Alternative input for direct control of VTTOUT and
VREFOUT.
Shutdown. This active low shutdown turns off both VTT and
VREFOUT. This pin has an internal pull-down, and must be
externally driven high for the IC to be on.
Signal Ground.
Buffered Voltage Reference Output.
VDDQ Input. Attach this pin to the VDDQ supply to generate
VTT and VREFOUT.
No Internal Connection
Connect PAD to Vss Ground Plane
6
12
13
7
8
14
15
9, 16
PAD
PAD
12
13
14
VSSQ
VREFOUT
VDDQ
NC
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FAN1655 Rev. 1.1.5
FAN1655 3A DDR Bus Termination Regulator
Typical Application
VDDQ
VDD
VTTFORCE
470µF
1
2
3
4
5
6
7
8
10µF
16
15
14
FAN1655
13
12
11
10
9
1nF
10k
10µF
VREFOUT
SHDN
VTTSENSE
GND
100µF
6V
1nF
(connect to VTTFORCE
at the load)
GND
Figure 1. (eTSSOP pinout shown)
Typical Performance Characteristics
Quiescent Current vs. Temperature
9
7.5
V
REF
Output Change vs. I
REF
1.0
V
DD
= V
DDQ
= 2.5V
T
A
= 25˚C
0.5
QUIESCENT CURRENT (mA)
6
∆
V
REFOUT
(mV)
4.5
3
0
-0.5
1.5
0
-60
-1.0
-6
-40
-20
0
20
40
60
80
100 120
140
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
V
REF
LOAD CURRENT (mA)
AMBIENT TEMPERATURE (˚C)
Figure 2. Quiescent Current vs.
Ambient Temperature
Figure 3. Reference Output
Load Regulation
1.260
100.0
Current Pulse Duration (S)
1.255
V
TT
OUTPUT (V)
T
A
=70°C
1.250
10.0
T
A
=25°C
1.245
1.240
-3000
1.0
-2000
-1000
0
1000
2000
3000
1
1.5
2
2.5
3
V
TT
Load Current (mA)
Peak Load Current (A)
Figure 4. V
TT
Load Regulation
Figure 5. Maximum Non-Repetitive Output
Current vs. Pulse Width
(FAN1655M SO-14 Package)
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FAN1655 Rev. 1.1.5
FAN1655 3A DDR Bus Termination Regulator
Absolute Maximum Ratings
Supply Voltage VDD, VDDQ
Junction Temperature, T
J
Storage Temperature
Lead Soldering Temperature, 10 seconds
Power Dissipation, P
D
FAN1655M (SOIC-14)
FAN1655MTF (e-TSSOP)
FAN1655MP (MLP)
6V
150˚C
-65 to 150˚C
300˚C
1.4W
See “Power Dissipation
and Derating”
Recommended Operating Conditions
Parameter
Supply Voltage VDD
Supply Voltage VDDQ
Ambient Operating Temperature
VREFIN
Conditions
Min.
2.3
2.2
0
1.1
Typ.
2.5
2.5
1.25
Max.
3.6
3.0
125
1.5
Units
V
V
˚C
V
Electrical Characteristics
(VDD = VDDQ = 2.5V ± 0.2V, and T
A
= 25˚C using circuit in Figure 1, unless otherwise noted.)
The • denotes specifications which apply over the specified operating temperature range.
Parameter
VTT Output Voltage
Conditions
I
OUT
= 0A, VREFIN = open
VDDQ = 2.3V •
VDDQ = 2.5V •
VDDQ = 2.7V •
I
OUT
= ±2.1A, VREFIN = open
VDDQ = 2.3V
VDDQ = 2.5V
VDDQ = 2.7V
Min.
1.135
1.235
1.335
1.110
1.210
1.310
-50
±3.1
Typ.
1.150
1.250
1.350
1.150
1.250
1.350
0.3
Max.
1.165
1.265
1.365
1.190
1.290
1.390
50
Units
V
V
V
V
V
V
V/µS
µA
A
K
Ω
VTT Output Slew Rate
VTT Leakage Current
VTT Current Limit
VREFIN Input Impedance
VREFOUT Output Voltage
Cload = 10µF
SHDN = 0V
•
100
No load
VREFIN = 1.150V •
VREFIN = 1.250V •
VREFIN = 1.350V •
1.145
1.245
1.345
-5
-10
1.667
0.800
7.5
6
3
50
155
30
20
10
50
75
1.150
1.250
1.350
1.155
1.255
1.355
5
10
V
V
V
mA
µA
V
V
mA
µA
µA
µA
˚C
˚C
VREFOUT Output Current
VREFOUT Leakage Current
SHDN Logic High
SHDN Logic Low
IDD Supply Current
VDDQ Leakage Current
VDD Leakage Current
SHDN Input Current
Over-Temperature Shutdown
Over-Temperature Hysteresis
VDDQ = 2.3V
SHDN = 0V
•
•
•
•
No load, SHDN = 2.7V
SHDN = 0V
SHDN = 0V
SHDN = 2.7V
•
•
•
•
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FAN1655 Rev. 1.1.5
FAN1655 3A DDR Bus Termination Regulator
Applications Information
Output Capacitor selection
The JEDEC specification for DDR termination requires
that VTT stay within ±40mV of VREF, which must track
VDDQ/2 within 1%. During the initial load transient, the
output capacitor keeps the output within spec. To stay
within the 40mV window, the “load step” due to the load
transient current dropping across the output capacitor’s
ESR should be kept to around 25mV: where ESR <
25
-----
is given in m
Ω
, and
∆
I is the maximum load current.
-
∆I
For example, to handle a 3A maximum load transient,
the ESR should be no greater than 8m
Ω
. Furthermore,
the output capacitor must be able to hold the load in
spec while the regulator recovers (about 15µS). A mini-
mum value of 470µF is recommended.
The FAN1655 requires a minimum of 100µF of input
capacitance with a maximum ESR value of 100m
Ω
to
insure stability.
Power Dissipation and Derating
The maximum output current (sink or source) for a 1.25V
output is:
P
D
(
MAX
-
I
OUT
(
MAX
)
=
---------------------
)
1.25
where P
D(MAX)
is the maximum power dissipation which
is:
T
J
(
MAX
)
–
T
A
-
P
D
(
MAX
)
=
---------------------------------
θ
JA
where T
J(MAX)
is the maximum die temperature of the IC
and T
A
is the operating ambient temperature.
FAN1655 has an internal thermal limit at 150°C, which
defines T
J(MAX)
. For the SOIC-14 package,
θ
JA
is given
at 88°C/W. Using equation 2, the maximum dissipation
at T
A
= 25°C is 1.4W, which is its rated maximum dissi-
pation.
The e-TSSOP or MLP package, however, use the PCB
copper to cool the IC through the thermal pad on the
package bottom. For maximum dissipation, this pad
should be soldered to the PCB copper, with as much
copper area as possible surrounding it to cool the pack-
age. Thermal vias should be placed as close to the ther-
mal pad as possible to transfer heat to other layers of
copper on the PCB. With large areas of PCB copper for
heat sinking, a
θ
JA
of under 40°C/W can easily be
achieved.
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FAN1655 Rev. 1.1.5
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