• PLL clock driver for DDR (Double Data Rate) synchronous
DRAM applications
• Spread spectrum clock compatible
• Operating frequency: 60MHz to 220MHz
• Low jitter (cycle-to-cycle): ±50ps
• Distributes one differential clock input to four differential clock
outputs
• Enters low power mode and 3-state outputs when input CLK
signal is less than 20MHz or PWRDWN is low
• Operates from a 2.5V supply
• Consumes <200μA quiescent current
μ
• External feedback pins (FBIN,
FBIN)
are used to synchronize
outputs to input clocks
• Available in TSSOP package
DESCRIPTION:
The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer
that distributes one differential clock input pair(CLK,
CLK
) to four differential
output pairs (Y
[0:3]
, Y
[0:3]
) and one differential pair of feedback clock outputs
(FBOUT,
FBOUT).
When
PWRDWN
is high, the outputs switch in phase and
frequency with CLK. When
PWRDWN
is low, all outputs are disabled to a high-
impedance state (3-state), and the PLL is shut down (low-power mode). The
device also enters this low-power mode when the input frequency falls below
a suggested detection frequency that is below 20MHz (typical 10MHz). An input
frequency detection circuit detects the low-frequency condition, and after
applying a >20MHz input signal, this detection circuit reactivates the PLL and
enables the outputs.
When AV
DD
is tied to GND, the PLL is turned off and bypassed for test
purposes. The CSPT855 is also able to track spread spectrum clocking for
reduced EMI.
Since the CSPT855 is based on PLL circuitry, it requires a stabilization time
to achieve phase-lock of the PLL. This stabilization time is required following
power up.
APPLICATIONS:
• For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266),
PC2700 (DDR333), PC3200 (DDR400)
FUNCTIONAL BLOCK DIAGRAM
3
Y0
2
12
Y0
Y1
Y1
Y2
Y2
PWRDWN
AV
DD
24
9
POWERDOWN
AND TEST
LOGIC
13
17
16
26
Y3
27
Y3
FBOUT
FBOUT
CLK
CLK
FBIN
FBIN
6
7
19
PLL
23
22
20
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2008
Integrated Device Technology, Inc.
NOVEMBER 2008
DSC-6203/12
IDTCSPT855
2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DDQ
, AV
DD
Rating
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Input Clamp Current
Output Clamp Current
Max
–0.5 to +3.6
–0.5 to V
DDQ
+ 0.5
–0.5 to V
DDQ
+ 0.5
±50
±50
±50
±100
105.8
– 65 to +150
Unit
V
V
V
mA
mA
mA
mA
°C/W
°C
V
I(2)
V
O(2)
I
IK
(V
I
< 0 or
V
I
< V
DDQ
)
I
OK
(V
O
< 0 or
V
O
> V
DDQ
)
GND
Y
0
Y
0
V
DDQ
GND
CLK
CLK
V
DDQ
AV
DD
AGND
V
DDQ
Y
1
Y
1
GND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
Y
3
Y
3
V
DDQ
PWRDWN
FBIN
FBIN
V
DDQ
FBOUT
FBOUT
V
DDQ
Y
2
Y
2
GND
Continuous Output Current
I
O
(V
O
= 0 to V
DDQ
)
V
DDQ
or GND
θ
JA
(3)
T
STG
Continuous Current
Package Thermal Impedance
Storage Temperature Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed. This value is limited to 3.6V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
TSSOP
TOP VIEW
PIN DESCRIPTION
Pin Name
AGND
AV
DD
CLK,
CLK
FBIN,
FBIN
FBOUT,
FBOUT
GND
PWRDWN
V
DDQ
Y
[0:3]
Y
[0:3]
Pin Number
10
9
6, 7
22, 23
19, 20
1, 5, 14, 15, 28
24
4, 8, 11, 18, 21, 25
3, 12, 17, 26
2, 13, 16, 27
O
O
I
I
I
O
I/O
Ground for analog supply
Analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Control input to turn device in the power-down mode
I/O supply
Buffered output copies of input clock, CLK
Buffered output copies of input clock,
CLK
Description
2
IDTCSPT855
2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE
(1)
INPUTS
AV
DD
GND
GND
X
X
2.5V (nom)
2.5V (nom)
2.5V (nom)
PWRDWN
H
H
L
L
H
H
X
CLK
L
H
L
H
L
H
<20MHz
(2)
CLK
H
L
H
L
H
L
<20MHz
(2)
Y
L
H
Z
Z
L
H
Z
Y
H
L
Z
Z
H
L
Z
OUTPUTS
FBOUT
L
H
Z
Z
L
H
Z
FBOUT
H
L
Z
Z
H
L
Z
PLL
Bypassed/OFF
Bypassed/OFF
OFF
OFF
ON
ON
OFF
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
Z = High-Impedance OFF-State
X = Don't Care
2. Typically 10MHz.
RECOMMENDED OPERATING CONDITIONS
(1)
Symbol
AV
DD,
V
DDQ
V
IL
V
IH
Supply Voltage
Input Voltage LOW
Input Voltage HIGH
DC Input Signal Voltage
(2)
V
ID
V
O(X)
V
I(X)
I
OH
I
OL
SR
T
A
Differential Input Signal Voltage
(3)
Output Differential Cross-Voltage
(4)
Input Differential Pair Cross-Voltage
(4)
HIGH-Level Output Current
LOW-Level Output Current
Input Slew Rate, see figure 8
Operating Free-Air Temperature
Commercial
Industrial
CLK, FBIN
CLK,
CLK,
FBIN,
FBIN
PRWDWN
CLK,
CLK,
FBIN,
FBIN
PRWDWN
Parameter
Min.
2.3
—
- 0.3
V
DDQ
/2 + 0.18
1.7
- 0.3
0.36
V
DDQ
/2 - 0.2
V
DDQ
/2 - 0.2
—
—
1
0
-40
Typ.
—
—
—
—
—
—
—
V
DDQ
/2
—
—
—
—
—
—
Max.
2.7
V
DDQ
/2 - 0.18
0.7
—
V
DDQ
+ 0.3
V
DDQ
V
DDQ
+ 0.6
V
DDQ
/2 + 0.2
V
DDQ
/2 + 0.2
- 12
12
4
+70
+85
V
V
V
V
mA
mA
V/ns
V
Unit
V
V
°
C
NOTES:
1. Unused inputs must be held HIGH or LOW to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential input signal voltage specifies the differential voltage | V
TR
- V
CP
| required for switching, where V
TR
is the true input level and V
CP
is the complementary input level.
4. Differential cross-point voltage is expected to track variations of V
DDQ
and is the voltage at which the differential signals must be crossing.
3
IDTCSPT855
2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C; Industrial: T
A
= –40°C to +85°C
Symbol
V
IK
V
OH
V
OL
I
OH
I
OL
V
OD
V
OX
I
I
I
OZ
I
DD(PD)
I
DD
AI
DD
C
I
C
O
Parameter
Input Voltage (All Inputs)
HIGH-Level Output Voltage
LOW-Level Output Voltage
HIGH-Level Output Current
LOW-Level Output Current
Output Voltage Swing
Output Differential Cross Voltage
Input Current
High-Impedance State Output Current
Power-Down Current on V
DDQ
and A
VDD
Dynamic Current on V
DDQ
Supply Current on A
VDD
Input Capacitance
Output Capacitance
C
L
= 14pF
C
L
= 0pF
(2)
Conditions
V
DDQ
= 2.3V, I
I
= -18mA
V
DDQ
= Min. to Max., I
OH
= -1mA
V
DDQ
= 2.3V, I
OH
= -12mA
V
DDQ
= Min. to Max., I
OL
= 1mA
V
DDQ
= 2.3V, I
OL
= 12mA
V
DDQ
= 2.3V, V
O
= 1V
V
DDQ
= 2.3V, V
O
= 1.2V
Differential outputs are terminated with 120Ω
Differential outputs are terminated with 120Ω
V
DDQ
= 2.7V, V
I
= 0V to 2.7V
V
DDQ
= 2.7V, V
O
= V
DDQ
or GND
CLK and
CLK
= 0MHz,
PWRDWN
= LOW,
Σ
of I
DD
and AI
DD
f
O
= 167MHz, Differential outputs terminated with 120Ω
f
O
= 167MHz, Differential outputs terminated with 120Ω
f
O
= 167MHz
V
DDQ
= 2.5V, V
I
= V
DDQ
or GND
V
DDQ
= 2.5V, V
I
= V
DDQ
or GND
Min.
—
V
DDQ
– 0.1
1.7
—
—
– 18
26
1.1
V
DDQ
/2 – 0.2
—
—
—
—
—
—
2
2.5
Typ.
(1)
—
—
—
—
—
– 32
35
—
V
DDQ
/2
—
—
100
150
130
8
2.5
3
Max.
– 1.2
—
—
0.1
0.6
—
—
V
DDQ
– 0.4
V
DDQ
/2 + 0.2
±10
±10
200
180
160
10
3
3.5
Unit
V
V
V
mA
mA
V
V
μA
μA
μA
mA
mA
pF
pF
NOTES:
1. All typical values are at respective nominal V
DDQ
.
2. Differential cross-point voltage is expected to track variation of V
DDQ
and is the voltage at which the differential signals must be crossing.
TIMING REQUIREMENTS
Symbol
f
CLK
t
DC
t
L
t
L
Parameter
Operating Clock Frequency
Input Clock Duty Cycle
Stabilization Time (PLL Mode)
(1)
Stabilization Time (Bypass Mode)
(2)
Min.
60
40
—
—
Max.
220
60
10
30
Unit
MHz
%
μs
ns
NOTES:
1. Recovery time required when the device goes from power-down mode into bypass mode (test mode with AV
DD
at GND).
2. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference
signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are
not applicable. This parameter does not apply for input modulation under SSC application.
4
IDTCSPT855
2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS
Symbol
t
PLH(2)
t
PHL(2)
t
JIT(PER)(3)
t
JIT(CC)(3)
t
JIT(HPER)(3)
Description
LOW to HIGH Level Propagation Delay Time
HIGH to LOW Level Propagation Delay Time
Jitter (period), see figure 6
Jitter (cycle-to-cycle), see figure 2
Half-Period Jitter, see figure 7
Test Conditions
Test mode, CLK to any output
Test mode, CLK to any output
66MHz
100/ 133/ 167/ 200 MHz
66MHz
100/ 133/ 167/ 200 MHz
66MHz
100MHz
133/ 167/ 200 MHz
t
SLR(O)
Output Clock Slew Rate (single-ended), see figure 8
Load: 120Ω / 14pF
Load: 120Ω / 4pF
66MHz
SSC Off
t
D(∅)(3)
Dynamic Phase Offset (includes jitter)
see figure 4
SSC On
t
(∅)
Static Phase Offset, see figure 3
100/ 133 MHz
167/ 200 MHz
66MHz
100/ 133 MHz
167/ 200 MHz
66MHz
100/ 133/ 167 MHz
200MHz
t
SK(O)(4)
t
R,
t
F
Output Skew, see figure 5
Output Rise and Fall Times (20% to 80%)
Load: 120Ω / 14pF
Min.
—
—
– 55
– 35
– 60
– 50
– 130
– 90
– 75
1
1
– 180
– 130
– 90
– 230
– 170
– 100
– 150
– 100
– 50
—
650
Typ.
(1)
4.5
4.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
—
55
35
60
50
130
90
75
2
3
180
130
90
230
170
100
150
100
50
50
900
ps
ps
ps
ps
V/ns
ps
ps
Unit
ns
ns
ps
NOTES:
1. All typical values are at respective nominal V
DDQ
.
2. Refers to transition of non-inverting output.
3. This parameter guaranteed by design but not production tested.
4. All differential output pins are terminated with 120Ω / 14pF.
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