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MC100EP52DTR2

Description
Flip Flops 3.3V/5V ECL D-Type
Categorylogic    logic   
File Size150KB,12 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
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MC100EP52DTR2 Overview

Flip Flops 3.3V/5V ECL D-Type

MC100EP52DTR2 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerON Semiconductor
Parts packaging codeSOIC
package instructionPLASTIC, TSSOP-8
Contacts8
Reach Compliance Codenot_compliant
Other featuresNECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
series100E
JESD-30 codeS-PDSO-G8
JESD-609 codee0
length3 mm
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Sup4000000000 Hz
Humidity sensitivity level1
Number of digits1
Number of functions1
Number of terminals8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP8,.19
Package shapeSQUARE
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)240
power supply-4.5 V
Maximum supply current (ICC)47 mA
Prop。Delay @ Nom-Sup0.41 ns
propagation delay (tpd)0.38 ns
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyECL
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Trigger typePOSITIVE EDGE
width3 mm
MC10EP52, MC100EP52
3.3V / 5V ECL Differential
Data and Clock D Flip-Flop
Description
The MC10EP/100EP52 is a differential data, differential clock D
flip−flop. The device is pin and functionally equivalent to the EL52
device.
Data enters the master portion of the flip−flop when the clock is
LOW and is transferred to the slave, and thus the outputs, upon a
positive transition of the clock. The differential clock inputs of the
EP52 allow the device to also be used as a negative edge triggered
device.
The EP52 employs input clamping circuitry so that under open input
conditions (pulled down to V
EE
) the outputs of the device will remain
stable.
The 100 Series contains temperature compensation.
Features
http://onsemi.com
MARKING
DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
1
HEP52
ALYW
G
8
KEP52
ALYW
G
8
1
5T MG
G
DFN8
MN SUFFIX
CASE 506AA
H
K
5T
3O
= MC10
= MC100
= MC10
= MC100
1
4
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2008
August, 2008
Rev. 7
1
Publication Order Number:
MC10EP52/D
3OMG
G
4
330 ps Typical Propagation Delay
Maximum Frequency
u
4 GHz Typical
PECL Mode: V
CC
= 3.0 V to 5.5 V with V
EE
= 0 V
NECL Mode: V
CC
= 0 V with V
EE
=
−3.0
V to
−5.5
V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at V
EE
Pb−Free Packages are Available
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
HP52
ALYWG
G
8
KP52
ALYWG
G
1
1

MC100EP52DTR2 Related Products

MC100EP52DTR2 MC10EP52DR2 MC10EP52DT MC100EP52DT
Description Flip Flops 3.3V/5V ECL D-Type Flip Flops 3.3V/5V ECL D-Type Flip Flops 3.3V/5V ECL D-Type Flip Flops 3.3V/5V ECL D-Type
Is it Rohs certified? incompatible incompatible incompatible incompatible
Parts packaging code SOIC SOIC SOIC SOIC
package instruction PLASTIC, TSSOP-8 SOIC-8 TSSOP, TSSOP8,.19 TSSOP, TSSOP8,.19
Contacts 8 8 8 8
Reach Compliance Code not_compliant not_compliant not_compliant not_compliant
Other features NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
series 100E 10E 10E 100E
JESD-30 code S-PDSO-G8 R-PDSO-G8 S-PDSO-G8 S-PDSO-G8
JESD-609 code e0 e0 e0 e0
length 3 mm 4.9 mm 3 mm 3 mm
Logic integrated circuit type D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
Maximum Frequency@Nom-Sup 4000000000 Hz 4000000000 Hz 4000000000 Hz 4000000000 Hz
Number of digits 1 1 1 1
Number of functions 1 1 1 1
Number of terminals 8 8 8 8
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C
Output polarity COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP SOP TSSOP TSSOP
Encapsulate equivalent code TSSOP8,.19 SOP8,.25 TSSOP8,.19 TSSOP8,.19
Package shape SQUARE RECTANGULAR SQUARE SQUARE
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing TAPE AND REEL TAPE AND REEL RAIL RAIL
Peak Reflow Temperature (Celsius) 240 240 240 240
power supply -4.5 V -5.2 V -5.2 V -4.5 V
Maximum supply current (ICC) 47 mA 47 mA 47 mA 47 mA
Prop。Delay @ Nom-Sup 0.41 ns 0.41 ns 0.41 ns 0.41 ns
propagation delay (tpd) 0.38 ns 0.38 ns 0.38 ns 0.38 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.1 mm 1.75 mm 1.1 mm 1.1 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 3 V 3 V 3 V 3 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES
technology ECL ECL ECL ECL
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn90Pb10) Tin/Lead (Sn90Pb10)
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 1.27 mm 0.65 mm 0.65 mm
Terminal location DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 30 30 30
Trigger type POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
width 3 mm 3.9 mm 3 mm 3 mm
Maker ON Semiconductor - ON Semiconductor ON Semiconductor

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