GS8170DW72AGC-250 datasheet, PDF

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GS8170DW72AGC-250: Description18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM; Categorystorage storage; File Size755KB，32 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS8170DW72AGC-250 Overview

18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM

GS8170DW72AGC-250 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	14 X 22 MM, 1 MM PITCH, LEAD FREE, BGA-209
Contacts	209
Reach Compliance Code	compli
ECCN code	3A991.B.2.B
Maximum access time	2.1 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B209
JESD-609 code	e1
length	22 mm
memory density	18874368 bi
Memory IC Type	STANDARD SRAM
memory width	72
Humidity sensitivity level	3
Number of functions	1
Number of terminals	209
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX72
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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GS8170DW36/72AC-350/333/300/250

209-Bump BGA

Commercial Temp

Industrial Temp

Features

• Double Late Write mode, Pipelined Read mode

• JEDEC-standard SigmaRAM

™

pinout and package

• 1.8 V +150/–100 mV core power supply

• 1.8 V CMOS Interface

• ZQ controlled user-selectable output drive strength

• Dual Cycle Deselect

• Burst Read and Write option

• Fully coherent read and write pipelines

• Echo Clock outputs track data output drivers

• Byte write operation (9-bit bytes)

• 2 user-programmable chip enable inputs

• IEEE 1149.1 JTAG-compliant Serial Boundary Scan

• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package

• Pin-compatible with future 36Mb, 72Mb, and 144Mb

devices

• Pb-Free 209-bump BGA package available

18Mb

1x1Dp CMOS I/O

Double Late Write SigmaRAM™

250 MHz–350 MHz

1.8 V V

1.8 V I/O

Bottom View

209-Bump, 14 mm x 22 mm BGA

1 mm Bump Pitch, 11 x 19 Bump Array

SigmaRAM Family Overview

GS8170DW36/72A SigmaRAMs are built in compliance with

the SigmaRAM pinout standard for synchronous SRAMs.

They are 18,874,368-bit (18Mb) SRAMs. This family of wide,

very low voltage CMOS I/O SRAMs is designed to operate at

the speeds needed to implement economical high performance

networking systems.

Functional Description

Because SigmaRAMs are synchronous devices, address data

inputs and read/write control inputs are captured on the rising

edge of the input clock. Write cycles are internally self-timed

and initiated by the rising edge of the clock input. This feature

eliminates complex off-chip write pulse generation required by

asynchronous SRAMs and simplifies input signal timing.

RAMs support pipelined reads utilizing a rising-edge-

triggered output register. They also utilize a Dual Cycle

Deselect (DCD) output deselect protocol.

RAMs are offered in a number of configurations including

Late Write, Double Late Write, and Double Data Rate (DDR).

The logical differences between the protocols employed by

these RAMs mainly involve various approaches to write

cueing and data transfer rates. The

ΣRAM

™

family standard

allows a user to implement the interface protocol best suited to

the task at hand.

RAMs are implemented with high performance CMOS

technology and are packaged in a 209-bump BGA.

Parameter Synopsis

Key Fast Bin Specs

Cycle Time

Access Time

Symbol

tKHKH

tKHQV

- 350

2.86 ns

1.7 ns

Rev: 1.04 4/2005

1/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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