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74HC138D(BJ)

Description
Decoder/Demultiplexer Single 3-to-8 16-Pin SOIC T/R
File Size227KB,9 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
Environmental Compliance
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74HC138D(BJ) Overview

Decoder/Demultiplexer Single 3-to-8 16-Pin SOIC T/R

74HC138D(BJ) Parametric

Parameter NameAttribute value
EU restricts the use of certain hazardous substancesCompliant
ECCN (US)EAR99
Part StatusActive
HTS8542.39.00.01
Logic FamilyHC
Logic FunctionDecoder/Demultiplexer
Demultiplexing Capability1-of-8
Number of Elements per Chip1
Number of Element Inputs3
Number of Input Enables per Element3
Number of Element Outputs8
Number of Output Enables per Element0
PolarityInverting
Maximum Propagation Delay Time @ Maximum CL (ns)26@6V|30@4.5V|150@2V
Absolute Propagation Delay Time (ns)225
Process TechnologyCMOS
Maximum Low Level Output Current (mA)5.2
Maximum High Level Output Current (mA)-5.2
Minimum Operating Supply Voltage (V)2
Typical Operating Supply Voltage (V)5
Maximum Operating Supply Voltage (V)6
Maximum Quiescent Current (mA)0.004
Propagation Delay Test Condition (pF)50
Minimum Operating Temperature (°C)-40
Maximum Operating Temperature (°C)125
PackagingTape and Reel
Supplier PackageSOIC
Pin Count16
Standard Package NameSOP
MountingSurface Mount
Package Height1.38
Package Length10.2(Max)
Package Width3.9
PCB changed16
Lead ShapeGull-wing
74HC138D
CMOS Digital Integrated Circuits Silicon Monolithic
74HC138D
1. Functional Description
3-to-8 Line Decoder
2. General
The 74HC138D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C
2
MOS technology.
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power
dissipation.
When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs (Y0 - Y7)
will go low.
When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all
outputs go high.
G1, G2A, and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory
systems.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
3. Features
(1)
(2)
(3)
(4)
High speed: t
pd
= 16 ns (typ.) at V
CC
= 5 V
Low power dissipation: I
CC
= 4.0
µA
(max) at T
a
= 25
Balanced propagation delays: t
PLH
t
PHL
Wide operating voltage range: V
CC(opr)
= 2.0 to 6.0 V
4. Packaging
SOIC16
Start of commercial production
©2016 Toshiba Corporation
1
2016-03
2016-08-04
Rev.3.0

74HC138D(BJ) Related Products

74HC138D(BJ) 74HC138D
Description Decoder/Demultiplexer Single 3-to-8 16-Pin SOIC T/R Decoder/Demultiplexer Single 3-to-8 16-Pin SOIC T/R
EU restricts the use of certain hazardous substances Compliant Compliant
ECCN (US) EAR99 EAR99
Part Status Active Active
HTS 8542.39.00.01 8542.39.00.01
Logic Family HC HC
Logic Function Decoder/Demultiplexer Decoder/Demultiplexer
Demultiplexing Capability 1-of-8 1-of-8
Number of Elements per Chip 1 1
Number of Element Inputs 3 3
Number of Input Enables per Element 3 3
Number of Element Outputs 8 8
Polarity Inverting Inverting
Maximum Propagation Delay Time @ Maximum CL (ns) 26@6V|30@4.5V|150@2V 150@2V|30@4.5V|26@6V
Absolute Propagation Delay Time (ns) 225 225
Process Technology CMOS CMOS
Maximum Low Level Output Current (mA) 5.2 5.2
Maximum High Level Output Current (mA) -5.2 -5.2
Minimum Operating Supply Voltage (V) 2 2
Typical Operating Supply Voltage (V) 5 5
Maximum Operating Supply Voltage (V) 6 6
Maximum Quiescent Current (mA) 0.004 0.004
Propagation Delay Test Condition (pF) 50 50
Minimum Operating Temperature (°C) -40 -40
Maximum Operating Temperature (°C) 125 125
Packaging Tape and Reel Tape and Reel
Supplier Package SOIC SOIC
Pin Count 16 16
Standard Package Name SOP SOP
Mounting Surface Mount Surface Mount
Package Height 1.38 1.38
Package Length 10.2(Max) 10.2(Max)
Package Width 3.9 3.9
PCB changed 16 16
Lead Shape Gull-wing Gull-wing
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