82V2042EPF datasheet, PDF - EEWORLD Datasheet

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82V2042EPF: DescriptionTelecom Interface ICs 3.3V DUAL LH LIU; CategoryWireless rf/communication Telecom circuit; File Size799KB，83 Pages; ManufacturerIDT (Integrated Device Technology)

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82V2042EPF Overview

Telecom Interface ICs 3.3V DUAL LH LIU

82V2042EPF Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	TQFP-80
Contacts	80
Reach Compliance Code	not_compliant
ECCN code	EAR99
JESD-30 code	S-PQFP-G80
JESD-609 code	e0
length	14 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	80
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP80,.64SQ
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum slew rate	0.18 mA
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	PCM TRANSCEIVER
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm

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DUAL CHANNEL T1/E1/J1 SHORT

HAUL LINE INTERFACE UNIT

FEATURES:

•

Dual channel T1/E1/J1 short haul line interfaces

Supports HPS (Hitless Protection Switching) for 1+1 protection

without external relays

Programmable T1/E1/J1 switchability allowing one bill of ma-

terial for any line condition

Single 3.3 V power supply with 5 V tolerance on digital interfaces

Meets or exceeds specifications in

- ANSI T1.102, T1.403 and T1.408

- ITU I.431, G.703, G.736, G.775 and G.823

- ETSI 300-166, 300-233 and TBR12/13

- AT&T Pub 62411

Software programmable or hardware selectable on:

- Wave-shaping templates

- Line terminating impedance (T1:100

Ω,

J1:110

Ω,

E1: 75

Ω/120 Ω)

- Adjustment of arbitrary pulse shape

- JA (Jitter Attenuator) position (receive path or transmit path)

- Single rail/dual rail system interfaces

- B8ZS/HDB3/AMI line encoding/decoding

- Active edge of transmit clock (TCLK) and receive clock (RCLK)

- Active level of transmit data (TDATA) and receive data (RDATA)

- Receiver or transmitter power down

- High impedance setting for line drivers

IDT82V2042E

•

- PRBS (Pseudo Random Bit Sequence) generation and detection

with 2

-1 PRBS polynomials for E1

- QRSS (Quasi Random Sequence Signals) generation and detection

with 2

-1 QRSS polynomials for T1/J1

- 16-bit BPV (Bipolar Pulse Violation) / Excess Zero/ PRBS or QRSS

error counter

- Analog loopback, Digital loopback, Remote loopback and Inband

loopback

Adaptive receive sensitivity up to -20 dB (Host Mode only)

Non-intrusive monitoring per ITU G.772 specification

Short circuit protection and internal protection diode for line

drivers

LOS (Loss Of Signal) detection with programmable LOS levels

(Host Mode only)

AIS (Alarm Indication Signal) detection

JTAG interface

Supports serial control interface, Motorola and Intel Non-Multi-

plexed interfaces and hardware control mode

Pin compatible to 82V2082 T1/E1/J1 Long Haul/Short Haul LIU

and 82V2052E E1 Short Haul LIU

Available in 80-pin TQFP

Green package options available

DESCRIPTION:

The IDT82V2042E can be configured as a dual channel T1, E1 or J1 Line

Interface Unit. The IDT82V2042E performs clock/data recovery, AMI/

B8ZS/HDB3 line decoding and detects and reports the LOS conditions. An

integrated Adaptive Equalizer is available to increase the receive sensitivity

and enable programming of LOS levels. In transmit path, there is an AMI/

B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter Attenuator,

which can be placed in either the receive path or the transmit path. The Jitter

Attenuator can also be disabled. The IDT82V2042E supports both Single

Rail and Dual Rail system interfaces. To facilitate the network maintenance,

a PRBS/QRSS generation/detection circuit is integrated in the chip, and dif-

ferent types of loopbacks can be set according to the applications. Four dif-

ferent kinds of line terminating impedance, 75

Ω,100 Ω,

110

Ω

and 120

Ω

are selectable on a per channel basis. The chip also provides driver short-

circuit protection and internal protection diode and supports JTAG bound-

ary scanning. The chip can be controlled by either software or hardware.

The IDT82V2042E can be used in LAN, WAN, Routers, Wireless Base

Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,

CSU/DSU equipment, etc.

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.



2005 Integrated Device Technology, Inc.

December 12, 2005

DSC-6774/1

Table of Contents

IDT82V2042E PIN CONFIGURATIONS ....................................................................................... 9

PIN DESCRIPTION ..................................................................................................................... 10

FUNCTIONAL DESCRIPTION .................................................................................................... 18

3.1

CONTROL MODE SELECTION ....................................................................................... 18

3.2

T1/E1/J1 MODE SELECTION .......................................................................................... 18

3.3

TRANSMIT PATH ............................................................................................................. 18

3.3.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 18

3.3.2 ENCODER .............................................................................................................. 18

3.3.3 PULSE SHAPER .................................................................................................... 18

3.3.3.1 Preset Pulse Templates .......................................................................... 18

3.3.3.2 User-Programmable Arbitrary Waveform ................................................ 20

3.3.4 TRANSMIT PATH LINE INTERFACE..................................................................... 23

3.3.5 TRANSMIT PATH POWER DOWN ........................................................................ 23

3.4

RECEIVE PATH ............................................................................................................... 24

3.4.1 RECEIVE INTERNAL TERMINATION.................................................................... 24

3.4.2 LINE MONITOR ...................................................................................................... 25

3.4.3 ADAPTIVE EQUALIZER......................................................................................... 26

3.4.4 RECEIVE SENSITIVITY ......................................................................................... 26

3.4.5 DATA SLICER ........................................................................................................ 26

3.4.6 CDR (Clock & Data Recovery)................................................................................ 26

3.4.7 DECODER .............................................................................................................. 26

3.4.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 26

3.4.9 RECEIVE PATH POWER DOWN........................................................................... 26

3.4.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 27

3.5

JITTER ATTENUATOR .................................................................................................... 28

3.5.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 28

3.5.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 28

3.6

LOS AND AIS DETECTION ............................................................................................. 29

3.6.1 LOS DETECTION ................................................................................................... 29

3.6.2 AIS DETECTION .................................................................................................... 31

3.7

TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 32

3.7.1 TRANSMIT ALL ONES ........................................................................................... 32

3.7.2 TRANSMIT ALL ZEROS......................................................................................... 32

3.7.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 32

3.8

LOOPBACK ...................................................................................................................... 32

3.8.1 ANALOG LOOPBACK ............................................................................................ 32

3.8.2 DIGITAL LOOPBACK ............................................................................................. 32

December 12, 2005

Table of Contents

IDT82V2042E

DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT

3.9

3.10

3.11

3.12

3.13

3.14

3.15

3.16

3.8.3 REMOTE LOOPBACK............................................................................................ 33

3.8.4 INBAND LOOPBACK.............................................................................................. 34

3.8.4.1 Transmit Activate/Deactivate Loopback Code......................................... 34

3.8.4.2 Receive Activate/Deactivate Loopback Code.......................................... 34

3.8.4.3 Automatic Remote Loopback .................................................................. 35

ERROR DETECTION/COUNTING AND INSERTION ...................................................... 36

3.9.1 DEFINITION OF LINE CODING ERROR ............................................................... 36

3.9.2 ERROR DETECTION AND COUNTING ................................................................ 36

3.9.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 37

LINE DRIVER FAILURE MONITORING ........................................................................... 37

MCLK AND TCLK ............................................................................................................. 38

3.11.1 MASTER CLOCK (MCLK) ...................................................................................... 38

3.11.2 TRANSMIT CLOCK (TCLK).................................................................................... 38

MICROCONTROLLER INTERFACES ............................................................................. 39

3.12.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 39

3.12.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 39

INTERRUPT HANDLING .................................................................................................. 40

5V TOLERANT I/O PINS .................................................................................................. 41

RESET OPERATION ........................................................................................................ 41

POWER SUPPLY ............................................................................................................. 41

PROGRAMMING INFORMATION .............................................................................................. 42

4.1

4.2

Reserved Registers .......................................................................................................... 42

4.3

4.3.1 GLOBAL REGISTERS............................................................................................ 44

4.3.2 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 45

4.3.3 JITTER ATTENUATION CONTROL REGISTER ................................................... 45

4.3.4 TRANSMIT PATH CONTROL REGISTERS........................................................... 46

4.3.5 RECEIVE PATH CONTROL REGISTERS ............................................................. 48

4.3.6 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 49

4.3.7 INTERRUPT CONTROL REGISTERS ................................................................... 52

4.3.8 LINE STATUS REGISTERS ................................................................................... 55

4.3.9 INTERRUPT STATUS REGISTERS ...................................................................... 57

4.3.10 COUNTER REGISTERS ........................................................................................ 58

HARDWARE CONTROL PIN SUMMARY .................................................................................. 59

IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 61

6.1

JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 62

6.2

JTAG DATA REGISTER ................................................................................................... 62

6.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 62

6.2.2 BYPASS REGISTER (BR)...................................................................................... 62

6.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 62

Table of Contents

December 12, 2005

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