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IDT74ALVCH32373BF

Description
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD
File Size115KB,7 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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IDT74ALVCH32373BF Overview

3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD

IDT74ALVCH32373
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 32-BIT
TRANSPARENT D-TYPE
LATCH WITH 3-STATE
OUTPUTS AND BUS-HOLD
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• Available in 96-ball LFBGA package
IDT74ALVCH32373
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for Heavy Loads
The 32-bit transparent D-type latch is built using advanced dual metal
CMOS technology. The high-speed, low-power latch is ideal for temporary
storage of data. The device can be used for implementing memory address
latches, I/O ports, and bus drivers. The Output Enable and Latch Enable
controls are organized to operate each device as four 8-bit latches, two 16-
bit latches, or one 32-bit latch. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
The ALVCH32373 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH32373 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistor.
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1
OE
A3
3
OE
J3
1
LE
A4
3
LE
J4
D
1
A5
D
A2
3
D
1
J5
D
C
J2
C
1
Q
1
3
Q
1
TO SEVEN OTHER CHANNELS
T3
TO SEVEN OTHER CHANNELS
2
OE
H3
4
OE
2
LE
H4
4
LE
T4
2
D
1
E5
D
E2
4
D
1
2
Q
1
N5
D
C
N2
C
4
Q
1
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TO SEVEN OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
1
©2000 Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-4908/1

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Description 3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD 3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD
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