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Datasheet> All Categories > semiconductor> logic> IDT74FCT3807APYI
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IDT74FCT3807APYI

Description
FCT SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
Categorysemiconductor    logic   
File Size77KB，8 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT74FCT3807APYI Overview

FCT SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20

IDT74FCT3807APYI Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals20
Maximum operating temperature70 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage3.6 V
Minimum supply/operating voltage3 V
Rated supply voltage3.3 V
Processing package descriptionQSOP-20
stateDISCONTINUED
CraftsmanshipCMOS
packaging shapeRectangle
Package SizeSMALL OUTLINE, SHRINK PITCH
surface mountYes
Terminal formGULL WING
Terminal spacing0.6350 mm
terminal coatingtin lead
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelCOMMERCIAL
seriesFCT
Output characteristics3-ST
Enter conditionsstandard
Logic IC typeLow Skew Clock Driver
Number of inverted outputs0.0
Real output number10
propagation delay TPD4.3 ns
Maximum same-side bending0.3500 ns

Preview

Download Datasheet
IDT74FCT3807/A
3.3V CMOS 1-TO-10 CLOCK DRIVER
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
3.3V CMOS
1-TO-10 CLOCK DRIVER
IDT74FCT3807/A
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
DESCRIPTION:
0.5 MICRON CMOS Technology
Guaranteed low skew < 350ps (max.)
Very low duty cycle distortion < 350ps (max.)
High speed: propagation delay < 3ns (max.)
Very low CMOS power levels
TTL compatible inputs and outputs
1:10 fanout
Maximum output rise and fall time < 1.5ns (max.)
Low input capacitance: 4.5pF typical
V
CC
= 3.3V ± 0.3V
Inputs can be driven from 3.3V or 5V components
Available in SSOP, SOIC, and QSOP packages
The FCT3807/A 3.3V clock driver is built using advanced dual metal CMOS
technology. This low skew clock driver offers 1:10 fanout. The large fanout from
a single input reduces loading on the preceding driver and provides an efficient
clock distribution network. The FCT3807/A offers low capacitance inputs with
hysteresis for improved noise margins. Multiple power and grounds reduce
noise. Typical applications are clock and signal distribution.
NOTE: EOL for non-green parts to occur on 5/13/10 per
PDN U-09-01
FUNCTIONAL BLOCK DIAGRAM
O
1
PIN CONFIGURATION
IN
O
2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
O
10
O
9
GND
O
8
V
CC
O
7
GND
O
6
O
5
GND
O
1
O
3
V
CC
O
2
O
4
GND
O
3
O
5
IN
O
6
V
CC
O
4
GND
O
7
SOIC/ SSOP/ QSOP
TOP VIEW
O
8
O
9
O
10
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
1
c
2001 Integrated Device Technology, Inc.
DECEMBER 2009
DSC-4647/5

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