LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML
FANOUT BUFFER
ICS858020
Features
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Four differential CML outputs
One LVPECL differential clock input
IN/nIN pair can accept the following differential input levels:
LVPECL, LVDS, CML, SSTL
Maximum output frequency: 3.2GHz
Output skew: 30ps (maximum)
Part-to-part skew: 225ps (maximum)
Additive phase jitter, RMS: <0.3ps (typical)
Propagation delay: 600ps (maximum)
Operating voltage supply range:
V
CC
= 2.375V to 3.63V, V
EE
= 0V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
General Description
The ICS858020 is a high speed 1-to-4
Differential-to-Open-Collector Output Fanout Buffer
HiPerClockS™
and is a member of the HiPerClockS™ family of
high performance clock solutions from IDT. The
ICS858020 uses an open-collector output structure
which requires the termination of the output by 50
Ω
to V
CC
. The
ICS858020 is optimized for high speed and very low output skew,
making it suitable for use in demanding applications such as
SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel.
The internally terminated differential input and V
REF
_
AC
pin allow
other differential signal families such as LVDS, LVHSTL and Open
Collector Output (OC) to be easily interfaced to the input with
minimal use of external components. The ICS858020 is packaged
in a small 3mm x 3mm 16-pin VFQFN package which makes it
ideal for use in space-constrained applications.
ICS
Block Diagram
Q0
IN
V
T
nIN
Q1
V
REF_AC
nQ1
nQ0
Pin Assignment
nQ0
IN 1
V
T
2
16 15 14 13
12 Q1
11 nQ1
10 Q2
9 nQ2
5
V
EE
V
REF_AC
3
nIN 4
6
nQ3
7
Q3
Q2
nQ2
ICS858020
16-Lead VFQFN
3mm x 3mm x 0.925
mm package body
K Package
Top View
Q3
nQ3
IDT™ / ICS™
CML FANOUT BUFFER
1
ICS858020AK REV. A SEPTEMBER 11, 2008
V
CC
V
CC
V
EE
Q0
8
ICS858020
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-CML FANOUT BUFFER
Table 1. Pin Descriptions
Number
1
2
3
4
5, 16
6, 7
8, 13
9, 10
11, 12
14, 15
Name
IN
V
T
V
REF_AC
nIN
V
EE
nQ3, Q3
V
CC
nQ2, Q2
nQ1, Q1
nQ0, Q0
Type
Input
Input
Output
Input
Power
Output
Power
Output
Output
Output
Description
Non-inverting differential LVPECL clock input. This input internally terminates with 50
Ω
to
the V
T
pin.
Termination input.
Reference voltage for AC-coupled applications. This output biases to V
CC
– 1.38V.
Inverting differential LVPECL clock input. This input internally terminates with 50
Ω
to the V
T
pin.
Negative supply pins.
Differential output pair. CML interface levels.
Positive supply pins.
Differential output pair. CML interface levels.
Differential output pair. CML interface levels.
Differential output pair. CML interface levels.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Input Current, IN/nIN
V
T
Current, I
VT
Input Sink/Source, I
REF_AC
Operating Temperature Range, T
A
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
Rating
4.6V (CML mode, V
EE
= 0V)
-0.5V to V
CC
+ 0.5V
20mA
40mA
+50mA
+100mA
+0.5mA
-40°C to 85°C
-65°C to 150°C
51.5°C/W (0 lfpm)
DC Electrical Characteristics
Table 2A. Power Supply DC Characteristics,
V
CC
= 2.375V to 3.63V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.63
135
Units
V
mA
IDT™ / ICS™
CML FANOUT BUFFER
2
ICS858020AK REV. A SEPTEMBER 11, 2008
ICS858020
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-CML FANOUT BUFFER
Table 2B. DC Characteristics,
V
CC
= 2.375V to 3.63V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
T_IN
V
REF_AC
Parameter
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing; NOTE 1
Differential Input Voltage Swing
IN-to-V
T
Voltage
Reference Voltage
V
CC
– 1.5
V
CC
– 1.4
IN/nIN
IN/nIN
IN/nIN
Test Conditions
IN to V
T
Minimum
40
1.2
0
0.15
0.3
Typical
50
Maximum
60
V
CC
V
IH
– 0.15
2.8
3.4
1.5
V
CC
– 1.3
Units
Ω
V
V
V
V
V
V
NOTE 1: Refer to Parameter Measurement Information,
Input Voltage Swing Diagram.
Table 2C. CML DC Characteristics,
V
CC
= 2.375V to 3.63V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OUT
Parameter
Output High Voltage; NOTE 1
Output Voltage Swing
Test Conditions
Minimum
V
CC
– 0.020
325
650
40
Typical
V
CC
– 0.010
400
800
50
60
Maximum
V
CC
Units
V
mV
mV
V
DIFF_OUT
Differential Output Voltage Swing
R
OUT
Output Source Impedance
Ω
NOTE 1: Outputs terminated with 100
Ω
across differential output pair.
AC Electrical Characteristics
Table 3. AC Characteristics,
V
CC
= 0V; V
EE
= -3.6V to -2.375V or, V
CC
= 2.375V to 3.6V; V
EE
= 0V, T
A
= -40°C to 85°C
Parameter
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
t
R
/ t
F
Symbol
Output Frequency
Propagation Delay, Differential;
NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
155.52MHz @ 3.3V, Integration
Range: 12kHz – 20MHz
20% to 80%
60
<0.03
180
350
15
Test Conditions
Minimum
Typical
Maximum
3.2
575
30
225
Units
GHz
ps
ps
ps
fs
ps
All parameters characterized at
≤
1.2GHz unless otherwise noted.
R
L
= 100
Ω
after each output pair.
Parameter limits are design target specs.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™
CML FANOUT BUFFER
3
ICS858020AK REV. A SEPTEMBER 11, 2008
ICS858020
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-CML FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = <0.03ps (typical)
SSB Phase Noise dBc/Hz
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
IDT™ / ICS™
CML FANOUT BUFFER
4
ICS858020AK REV. A SEPTEMBER 11, 2008
ICS858020
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-CML FANOUT BUFFER
Parameter Measurement Information
0V
Qx
SCOPE
V
CC
CML Driver
V
EE
V
CC
V
CC
Power
Supply
nIN
V
PP
Cross Points
V
CMR
IN
-2.375V to -3.63V
V
EE
Open Collector Output Load AC Test Circuit
Differential Input Level
Par t 1
nQx
nQx
Qx
Qx
nQy
Qy
Par t 2
nQy
Qy
tsk(o)
tsk(pp)
Part-to-Part Skew
Output Skew
nIN
V
DIFF_IN
, V
DIFF_OUT
V
IN
, V
OUT
400mV
(typical)
800mV
(typical)
IN
nQ[0:3]
Q[0:3]
t
PD
Single-ended & Differential Input Voltage Swing
Propagation Delay
IDT™ / ICS™
CML FANOUT BUFFER
5
ICS858020AK REV. A SEPTEMBER 11, 2008
NXP MCU
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