1-to-10 Low Skew,
1, 2
LVCMOS/LVTTL
3.3V Fanout Buffer
Datasheet
87946I
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
General Description
The 87946I is a low skew, ÷1, ÷2 LVCMOS Fanout Buffer. The
87946I has two selectable single ended clock inputs. The 87946I
has two selectable single ended clock inputs. The single ended clock
inputs accept LVCMOS or LVTTL input levels. The low impedance
LVCMOS outputs are designed to drive 50 series or parallel
terminated transmission lines. The effective fanout can be increased
from 10 to 20 by utilizing the ability of the outputs to drive two series
terminated lines.
The divide select inputs, DIV_SELx, control the output frequency of
each bank. The outputs can be utilized in the ÷1, ÷2 or a combination
of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the
internal frequency dividers and also controls the active and high
impedance states of all outputs.
The 87946I is characterized at 3.3V core/3.3V output. Guaranteed
output and part-to-part skew characteristics make the 87946I ideal
for those clock distribution applications demanding well defined
performance and repeatability.
Features
•
•
•
•
•
•
•
•
•
Ten single-ended LVCMOS outputs, 7 typical output impedance
Selectable CLK0 and CLK1 LVCMOS clock inputs
CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
Maximum input/output frequency: 150MHz
Output skew: 350ps (maximum)
3.3V input, 3.3V outputs
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
For drop-in replacement use 87946i-147
Block Diagram
CLK_SEL
Pulldown
CLK0
Pullup
CLK1
Pullup
DIV_SELA
Pulldown
0
1
DIV_SELB
Pulldown
0
1
DIV_SELC
Pulldown
MR/nOE
Pulldown
3
Pin Assignment
MR/nOE
GND
GND
V
DDA
V
DDA
QA0
QA1
QA2
0
1
÷1
÷2
0
1
3
QA[0:2]
CLK_SEL
V
DD
CLK0
CLK1
QB[0:2]
DIV_SELA
DIV_SELB
DIV_SELC
GND
4
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
9
V
DDC
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
QC2
GND
GND
QC0
QC1
V
DDC
QC3
GND
QB0
V
DDB
QB1
GND
QB2
V
DDB
V
DDC
QC[0:3]
87946I
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision C, September 20, 2016
87946I Datasheet
Table 1. Pin Descriptions
Number
1
2
3, 4
5
6
7
8, 11, 15, 20,
24, 27, 31
9, 13, 17
10, 12,
14, 16
18, 22
19, 21, 23
25, 29
26, 28, 30
Name
CLK_SEL
V
DD
CLK0, CLK1
DIV_SELA
DIV_SELB
DIV_SELC
GND
V
DDC
QC0, QC1,
QC2, QC3
V
DDB
QB2, QB1, QB0
V
DDA
QA2, QA1, QA0
Input
Power
Input
Input
Input
Input
Power
Power
Output
Power
Output
Power
Output
Pullup
Pulldown
Pulldown
Pulldown
Type
Pulldown
Description
Clock select input. When HIGH, selects CLK1. When LOW, selects CLK0.
LVCMOS / LVTTL interface levels.
Positive supply pin.
LVCMOS/LVTTL clock inputs.
Controls frequency division for Bank A outputs.
LVCMOS/LVTTL interface levels.
Controls frequency division for Bank B outputs.
LVCMOS/LVTTL interface levels.
Controls frequency division for Bank C outputs.
LVCMOS/LVTTL interface levels.
Power supply ground.
Positive supply pins for Bank C outputs.
Bank C clock outputs. LVCMOS/LVTTL interface levels.
7
typical output impedance.
Positive supply pins for Bank B outputs.
Bank B clock outputs. LVCMOS/LVTTL interface levels.
7
typical output impedance.
Positive supply pins for Bank A outputs.
Bank A clock outputs. LVCMOS/LVTTL interface levels.
7
typical output impedance.
Pulldown
Master reset and output enable. When LOW, output drivers are enabled.
When HIGH, output drivers are in High-Impedance and dividers are reset.
LVCMOS / LVTTL interface levels.
32
MR/nOE
Input
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
51
51
V
DD
, V
DDX
= 3.6V
25
7
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
k
k
pF
R
PULLDOWN
Input Pulldown Resistor
C
PD
R
OUT
Power Dissipation Capacitance
(per output); NOTE 1
Output Impedance
NOTE 1: V
DDx
denotes V
DDA
, V
DDB
, V
DDC
.
© 2016 Integrated Device Technology, Inc
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Revision C, September 20, 2016
87946I Datasheet
Table 3. Function Table
Inputs
MR/nOE
1
0
0
0
0
0
0
DIV_SELA
X
0
1
X
X
X
X
DIV_SELB
X
X
X
0
1
X
X
DIV_SELC
X
X
X
X
X
0
1
QA0:QA2
High-Impedance
f
IN
/1
f
IN
/2
Active
Active
Active
Active
Outputs
QB0:QB2
High-Impedance
Active
Active
f
IN
/1
f
IN
/2
Active
Active
QC0:QC3
High-Impedance
Active
Active
Active
Active
f
IN
/1
f
IN
/2
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
DD
Outputs, V
DD
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDX
+ 0.5V
47.9C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDX
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDX
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage; NOTE 1
Power Supply Current
Test Conditions
Minimum
3.0
3.0
Typical
3.3
3.3
Maximum
3.6
3.6
85
Units
V
V
mA
NOTE 1:
V
DDX
denotes V
DDA
, V
DDB
, V
DDC.
©2016 Integrated Device Technology, Inc
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Revision C, September 20, 2016
87946I Datasheet
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDX
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
Parameter
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
MR/nOE
CLK0, CLK1
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
MR/nOE
CLK0, CLK1
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
MR/nOE
CLK0, CLK1
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
MR/nOE
CLK0, CLK1
V
OH
V
OL
Output High Voltage
Output Low Voltage
V
DD
= V
IN
= 3.6V
V
DD
= V
IN
= 3.6V
V
DD
= 3.6V, V
IN
= 0V
V
DD
= 3.6V, V
IN
= 0V
I
OH
= -20mA
I
OH
= 20mA
-5
-120
2.5
0.4
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
120
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
IH
Input High Voltage
V
IL
Input Low Voltage
I
IH
Input High Current
I
IL
Input Low Current
© 2016 Integrated Device Technology, Inc
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Revision C, September 20, 2016
87946I Datasheet
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= V
DDX
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
f
IN
tp
LH
tp
HL
tsk(o)
tsk(w)
tsk(pp)
t
R
/ t
F
t
EN
t
DIS
Parameter
Input Frequency
Propagation Delay
Low to High; NOTE 1
Propagation Delay
High to Low; NOTE 1
Output Skew; NOTE 2, 6
Multiple Frequency Skew;
NOTE 3, 6
Part-to-Part Skew;
NOTE 4, 6
Output Rise/Fall Time;
NOTE 5
Output Enable Time;
NOTE 5
Output Disable Time;
NOTE 5
0.8V to 2.0V
0.1
f
MAX
< 100MHz
f
MAX
> 100MHz
2
2.0
Test Conditions
Minimum
Typical
Maximum
150
12
11.5
350
350
450
4.5
1.0
11
11
Units
MHz
ns
ns
ps
ps
ps
ns
ns
ns
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: V
DDX
denotes V
DDA
, V
DDB
, V
DDC.
NOTE 1: Measured from V
DD
/2 of the input to V
DDX
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDX
/2.
NOTE 3: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V
DDX
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
5
Revision C, September 20, 2016
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