and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html.
Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012
Subscribe
1–2
Chapter 1: Overview for the Arria II Device Family
Arria II Device Feature
■
Complete PIPE protocol solution with an embedded hard IP block that provides
physical interface and media access control (PHY/MAC) layer, Data Link layer,
and Transaction layer functionality
Optimized for high-bandwidth system interfaces
■
■
Up to 726 user I/O pins arranged in up to 20 modular I/O banks that support a
wide range of single-ended and differential I/O standards
High-speed LVDS I/O support with serializer/deserializer (SERDES) and
dynamic phase alignment (DPA) circuitry at data rates from 150 Mbps to
1.25 Gbps
■
■
Low power
■
■
Architectural power reduction techniques
Typical physical medium attachment (PMA) power consumption of 100 mW at
3.125 Gbps.
Power optimizations integrated into the Quartus II development software
■
■
Advanced usability and security features
■
■
Parallel and serial configuration options
On-chip series (R
S
) and on-chip parallel (R
T
) termination with auto-calibration
for single-ended I/Os and on-chip differential (R
D
) termination for differential
I/O
256-bit advanced encryption standard (AES) programming file encryption for
design security with volatile and non-volatile key storage options
Robust portfolio of IP for processing, serial protocols, and memory interfaces
Low cost, easy-to-use development kits featuring high-speed mezzanine
connectors (HSMC)
■
■
■
■
Emulated LVDS output support with a data rate of up to 1152 Mbps
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation
Table 1–1
lists the Arria II device features.
Table 1–1. Features in Arria II Devices
Arria II GX Devices
Feature
EP2AGX45
Total Transceivers
(1)
ALMs
LEs
PCIe hard IP blocks
M9K Blocks
M144K Blocks
Total Embedded Memory in M9K
Blocks (Kbits)
Total On-Chip Memory
(M9K +M144K + MLABs) (Kbits)
Embedded Multipliers (18 x 18)
(2)
General Purpose PLLs
8
18,050
42,959
1
319
—
2,871
3,435
232
4
2 or 4
6
EP2AGX65
8
25,300
60,214
1
495
—
4,455
5,246
312
4
2 or 4
6
EP2AGX95
12
37,470
89,178
1
612
—
5,508
6,679
448
6
4 or 6
8
24, 28, or 32
EP2AGX125
12
49,640
118,143
1
730
—
6,570
8,121
576
6
4 or 6
8
24, 28, 32
EP2AGX190
16
76,120
181,165
1
840
—
7,560
9,939
656
6
6 or 8
12
28 or 48
EP2AGX260
16
102,600
244,188
1
950
—
8,550
11,756
736
6
6 or 8
12
24 or 48
EP2AGZ225
16 or 24
89,600
224,000
1
1,235
—
11,115
13,915
800
6 or 8
8 or 12
16 or 20
42 or 86
EP2AGZ300
16 or 24
119,200
298,000
1
1,248
24
14,688
18,413
920
4, 6, or 8
8 or 12
8, 16, or 20
EP2AGZ350
16 or 24
139,400
348,500
1
1,248
36
16,416
20,772
1,040
4, 6, or 8
8 or 12
8, 16, or 20
Arria II GZ Devices
July 2012
Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 1: Overview for the Arria II Device Family
Arria II Device Feature
Transceiver TX PLLs
(3), (4)
User I/O Banks
(5), (6)
High-Speed LVDS SERDES
(up to 1.25 Gbps)
(7)
Notes to
Table 1–1:
8, 24, or 28 8, 24, or 28
0
(8),
42, or 86 0
(8),
42, or 86
(1) The total number of transceivers is divided equally between the left and right side of each device, except for the devices in the F780 package. These devices have eight transceiver channels located only on
the right side of the device.
(2) This is in four multiplier adder mode.
(3) The FPGA fabric can use these phase locked-loops (PLLs) if they are not used by the transceiver.
(4) The number of PLLs depends on the package. Transceiver transmitter (TX) PLL count = (number of transceiver blocks)
×
2.
(5) Banks 3C and 8C are dedicated configuration banks and do not have user I/O pins.
(6) For Arria II GZ devices, the user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins
are not included in the pin count.
(7) For Arria II GZ devices, total pairs of high-speed LVDS SERDES take the lowest channel count of RX/TX. For more information, refer to the
High-Speed I/O Interfaces and DPA in Arria II Devices
chapter.
(8) The smallest pin package (780-pin package) does not support high-speed LVDS SERDES.
1–3
1–4
Chapter 1: Overview for the Arria II Device Family
Arria II Device Feature
Table 1–2
and
Table 1–3
list the Arria II device package options and user I/O pin
counts, high-speed LVDS channel counts, and transceiver channel counts for Ultra
FineLine BGA (UBGA) and FineLine BGA (FBGA) devices.
Table 1–2. Package Options and I/O Information for Arria II GX Devices
358-Pin Flip Chip UBGA
17 mm x 17 mm
XCVRs
Device
I/O
LVDS
(8)
572-Pin Flip Chip FBGA
25 mm x 25 mm
XCVRs
I/O
LVDS
(8)
57(R
D
or
eTX) +
56(RX, TX,
or eTX)
57(R
D
or
eTX) +
56(RX, TX,
or eTX)
57(R
D
or
eTX) +
56(RX, TX,
or eTX)
57(R
D
or
eTX) +
56(RX,TX, or
eTX)
(Note 1), (2), (3), (4), (5), (6), (7)
780-Pin Flip Chip FBGA
29 mm x 29 mm
XCVRs
I/O
LVDS
(8)
85(R
D
or eTX)
+ 84(RX, TX,
or eTX)
85(R
D
or eTX)
+84(RX,TX,
eTX)
85(R
D
or eTX)
+84(RX, TX, or
eTX)
85(R
D
or eTX)
+84(RX,TX, or
eTX)
1152-Pin Flip Chip FBGA
35 mm x 35 mm
I/O
LVDS
(8)
XCVRs
—
—
12
12
16
16
EP2AGX45
33(R
D
or eTX)
156 + 32(RX, TX,
or eTX)
33(R
D
or eTX)
156 + 32(RX, TX,
or eTX)
4
252
8
364
8
—
—
EP2AGX65
4
252
8
364
8
—
—
EP2AGX95
—
—
—
260
8
372
12
105(R
D
or
eTX) +
452
104(RX, TX, or
eTX)
105(R
D
or
eTX) +
452
104(RX, TX, or
eTX)
145(R
D
or
eTX) +
612
144(RX, TX, or
eTX)
145(R
D
, eTX) +
612 144(RX, TX, or
eTX)
EP2AGX125
—
—
—
260
8
372
12
EP2AGX190
—
—
—
—
—
—
85(R
D
or eTX)
372 +84(RX, TX, or
eTX)
85(R
D
, eTX)
372 +84(RX, TX, or
eTX)
12
EP2AGX260
—
—
—
—
—
—
12
Notes to
Table 1–2:
(1) The user I/O counts include clock pins.
(2) The arrows indicate packages vertical migration capability. Vertical migration allows you to migrate to devices whose dedicated pins, configuration pins,
and power pins are the same for a given package across device densities.
(3)
R
D
= True LVDS input buffers with on-chip differential termination (R
D
OCT) support.
(4) RX = True LVDS input buffers without R
D
OCT support.
(5) TX = True LVDS output buffers.
(6) eTX = Emulated-LVDS output buffers, either
LVDS_E_3R
or
LVDS_E_1R.
(7) The LVDS channel count does not include dedicated clock input pins and PLL clock output pins.
(8) These numbers represent the accumulated LVDS channels supported in Arria II GX row and column I/O banks.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation
Chapter 1: Overview for the Arria II Device Family
Arria II Device Feature
1–5
Table 1–3. Package Options and I/O Information for Arria II GZ Devices
780-Pin Flip Chip FBGA
29 mm x 29 mm
XCVRs
Device
I/O
EP2AGZ225
EP2AGZ300
EP2AGZ350
Notes to
Table 1–3:
(1) The user I/O counts include clock pins.
(Note 1), (2), (3), (4), (5)
1517-Pin Flip Chip FBGA
40 mm x 40 mm
XCVRs
I/O
734
734
734
LVDS
(7)
179 (RX or eTX) +
184 (TX or eTX)
179 (RX or eTX) +
184 (TX or eTX)
179 (RX or eTX) +
184 (TX or eTX)
XCVRs
24
24
24
1517-Pin Flip Chip
FBGA
—
—
—
—
—
—
C3, C4, I3, I4
C3, C4, I3, I4
C3, C4, I3, I4
1152-Pin Flip Chip FBGA
35 mm x 35 mm
I/O
554
554
554
LVDS
(7)
135 (RX or eTX) +
140 (TX or eTX)
135 (RX or eTX) +
140 (TX or eTX)
135 (RX or eTX) +
140 (TX or eTX)
LVDS
(6)
—
68 (RX or eTX) +
72 eTX
68 (RX or eTX) +
72 eTX
—
281
281
—
16
16
16
16
16
(2) RX = True LVDS input buffers without R
D
OCT support for row I/O banks, or true LVDS input buffers without R
D
OCT support for column I/O
banks.
(3) eTX = Emulated-LVDS output buffers, either
LVDS_E_3R
or
LVDS_E_1R.
(4) The LVDS RX and TX channels are equally divided between the left and right sides of the device.
(5) The LVDS channel count does not include dedicated clock input pins.
(6) For Arria II GZ 780-pin FBGA package, the LVDS channels are only supported in column I/O banks.
(7) These numbers represents the accumulated LVDS channels supported in Arria II GZ device row and column I/O banks.
Arria II devices are available in up to four speed grades: –3 (fastest), –4, –5, and –6
(slowest).
Table 1–4
lists the speed grades for Arria II devices.
Table 1–4. Speed Grades for Arria II Devices
Device
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGZ225
EP2AGZ300
EP2AGZ350
358-Pin Flip Chip
UBGA
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
—
—
—
—
—
—
—
572-Pin Flip Chip
FBGA
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
—
—
—
—
—
780-Pin Flip Chip
FBGA
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
—
C3, C4, I3, I4
C3, C4, I3, I4
1152-Pin Flip Chip
FBGA
—
—
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C3, C4, I3, I4
C3, C4, I3, I4
C3, C4, I3, I4
July 2012
Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration
京公网安备 11010802033920号
EEWORLD
