XRD54L08/L10/L12
May 2000-2
3V, Low Power, Voltage Output
Serial 8/10/12-Bit DAC Family
FEATURES
D
8/10/12-Bit Resolution
D
Operates from a Single 3V Supply
D
Buffered Voltage Output: 13ms Typical Settling Time
D
145mW Total Power Consumption (typ)
D
Guaranteed Monotonic Over Temperature
D
Flexible Output Range: 0V to V
DD
D
8 Lead SOIC and PDIP Package
D
Power On Reset
D
Serial Data Output for Daisy Chaining
APPLICATIONS
D
Digital Calibration
D
Battery Operated Instruments
D
Remote Industrial Devices
D
Cellular Telephones
D
Motion Control
D
VXCO Control
D
Comparator Level Setting
GENERAL DESCRIPTION
The XRD54L08/L10/L12 are low power, voltage output
digital-to-analog converters (DAC) for +3V power supply
operation. The parts draw only 50mA of quiescent current
and are available in both an 8-lead PDIP and SOIC
package.
The XRD54L08/L10/L12 have a 3 wire serial port with an
output allowing the user to daisy chain several of them
together. The serial port will support both Microwiret,
SPIt, and QSPIt standards.
The outputs of the XRD54L08/L10/L12 are set at a gain of
+2. The output short circuit current is 7mA typical.
ORDERING INFORMATION
Part No.
XRD54L08AID
XRD54L08AIP
XRD54L10AID
XRD54L10AIP
XRD54L12AID
XRD54L12AIP
Package
8 Lead 150 Mil JEDEC SOIC
8 Lead 300 Mil PDIP
8 Lead 150 Mil JEDEC SOIC
8 Lead 300 Mil PDIP
8 Lead 150 Mil JEDEC SOIC
8 Lead 300 Mil PDIP
Operating
Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Rev. 1.30
E2000
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
z
(510) 668-7000
z
(510) 668-7017
XRD54L08/L10/L12
BLOCK DIAGRAM
V
REFIN
2
n
Switch
Matrix
R
+
-
R
V
DD
V
OUT
AGND
V
DD
CS
SCLK
SDIN
Shift Register
Power On
Reset
DOUT
Figure 1. Block Diagram
PIN CONFIGURATION
SDIN
SCLK
CS
DOUT
1
2
3
4
8
7
6
5
V
DD
V
OUT
V
REFIN
AGND
SDIN
SCLK
CS
DOUT
1
2
3
4
8
7
6
5
V
DD
V
OUT
V
REFIN
AGND
8 Lead SOIC (Jedec, 0.150”)
8 Lead PDIP (0.300”)
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
Rev. 1.30
2
Symbol
SDIN
SCLK
CS
DOUT
AGND
V
REFIN
V
OUT
V
DD
Description
Serial Data Input
Serial Data Clock
Chip Select (Active High)
Serial Data Output
Analog Ground
Voltage Reference Input
DAC Output
Supply Voltage
XRD54L08/L10/L12
Test Conditions: V
DD
= 3V, GND= 0V, REFIN= 1.000V (External), R
L
= 10kW, C
L
= 100pF, T
A
= T
MIN
to T
MAX
,
Unless Otherwise Noted.
Symbol
N
INL
DNL
V
OS
TCV
OS
PSRR
GE
TCGE
PSRR
Parameter
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Offset Tempco
Offset-Error Power-Supply
Rejection Ratio
Gain Error
Gain-Error Tempco
Power-Supply
Rejection Ratio
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Offset Tempco
Offset-Error Power-Supply
Rejection Ratio
Gain Error
Gain-Error Tempco
Power-Supply
Rejection Ratio
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Offset Tempco
Offset-Error Power-Supply
Rejection Ratio
Gain Error
Gain-Error Tempco
Power-Supply
Rejection Ratio
0
12
2
0.5
3
2
1.0
0.1
10
0.1
1.25
1.25
0.4
4
-1
1.25
V
OS
TCV
OS
PSRR
GE
TCGE
PSRR
8
0
10
0.5
0.50
3
2
0.5
0.1
10
0.1
1.25
1
0.4
1
0.75
8
0
Min.
8
0.25
0.25
3
2
0.5
0.1
10
0.1
1.25
1
0.4
0.5
0.5
8
Typ.
Max.
Unit
Bits
LSB
±LSB
mV
ppm/°C
mV
%FS
ppm/°C
mV
2.5V
±
V
DD
±
3.5V, Measured at
FS
2.5V
±
V
DD
±
3.5V
Guaranteed Monotonic
Conditions
ELECTRICAL CHARACTERISTICS
Static Performance XRD54L08
Static Performance XRD54L10
N
INL
DNL
V
OS
TCV
OS
PSRR
GE
TCGE
PSRR
Bits
LSB
±LSB
mV
ppm/°C
mV
%FS
ppm/°C
mV
2.5V
±
V
DD
±
3.5V, Measured at
FS
2.5V
±
V
DD
±
3.5V
Guaranteed Monotonic
Static Performance XRD54L12
N
INL
DNL
Bits
LSB
LSB
LSB
mV
ppm/°C
mV
%FS
ppm/°C
mV
2.5V
±
V
DD
±
3.5V, Measured at
FS
2.5V
±
V
DD
±
3.5V
Guaranteed Monotonic
Rev. 1.30
3
XRD54L08/L10/L12
Test Conditions: V
DD
= 3V, GND= 0V, REFIN= 1.000V (External), R
L
= 10kW, C
L
= 100pF, T
A
= T
MIN
to T
MAX
,
Unless Otherwise Noted.
Symbol
V
O
V
REG
+I
SC
-I
SC
V
REFIN
R
IN
TCR
IN
C
IN
AC
FT
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
SR
t
s
D
FT
SINAD
Parameter
Output Voltage Range
Output Load Regulation
Short-Circuit Current, Sink
Short-Circuit Current, Source
Voltage Range
Input Resistance
Input Resistance Tempco
Input Capacitance
AC Feedthrough
Input High
Input Low
Input Current
Input Capacitance
Output High
Output Low
Voltage-Output Slew Rate
Voltage-Output Settling Time
Digital Feedthrough
Signal-to-Noise Plus Distortion
0.13
0.21
13
1
68
15
V
DD
-1
0.4
10
2.0
0.8
±1
0
40
65
1500
32
-80
40
Min.
0
2
11
2.5
V
DD
Typ.
Max.
V
DD
--0.4
ELECTRICAL CHARACTERISTICS
(CONT’D)
Unit
V
mV
mA
mA
V
kW
ppm/°C
pF
dB
V
V
mA
pF
V
V
V/ms
ms
nV-s
dB
Conditions
Voltage Output (V
OUT
) XRD54L08/L10/L12
4
V
OUT
= 2V, R
L
=2kW
V
OUT
= V
DD
V
OUT
= GND
Output Swing Limited, Not Code
Dependent
Voltage Reference Input (V
REFIN
) XRD54L08/L10/L12
Not Code Dependent
REFIN = 1kHz, 2Vp-p, SD
IN
=000h
Digital Inputs (SDIN, SCLK, CS) XRD54L08/L10/L12
V
IN
=0V or V
DD
Digital Output (DOUT) XRD54L08/L10/L12
I
SOURCE
=4mA
I
SINK
=4mA
T
A
=+25°C
±1/2LSB,
V
OUT
=2V
CS=V
DD
, SDIN=SCLK=100kHz
V
REFIN
=1kHz, 2Vp-p F.S.,
SDIN=Full Scale
--3dB BW=250kHz
Dynamic Performance XRD54L08/L10/L12
Power Supply XRD54L08/L10/L12
V
DD
I
DD
Positive Supply Voltage
Power Supply Current
2.5
35
3.5
60
V
mA
All Inputs=0V or V
DD
,
Output=No Load, V
O
=0V,
I
REF
Not Included
Switching Characteristics XRD54L08/L10/L12
t
CSS
t
CSH0
t
CSH1
CS Setup Time
SCLK Fall to CS Fall Hold Time
SCLK Fall to CS Rise Hold TIme
10
5
0
20
ns
ns
ns
Notes:
1
Total supply current consumption = I
DD
+ I
REF
+ (V
OUT
/ 70K.)
Rev. 1.30
4
XRD54L08/L10/L12
Test Conditions: V
DD
= 3V, GND= 0V, REFIN= 1.000V (External), R
L
= 10kW, C
L
= 100pF, T
A
= T
MIN
to T
MAX
,
Unless Otherwise Noted.
Symbol
t
CH
t
CL
t
DS
t
DH
t
DO
t
CSW
t
CS1
Parameter
SCLK High Width
SCLK Low Width
D
IN
Setup Time
D
IN
Hold Time
D
OUT
Valid Propagation Delay
CS High Pulse Width
CS Rise to SCLK Rise Setup
Time
20
10
Min.
20
20
10
0
8
40
20
15
Typ.
35
35
45
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
C
L
= 50pF
Conditions
ELECTRICAL CHARACTERISTICS
(CONT’D)
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, +5V
Digital Input Voltage to GND . . . . . . -0.3V, V
DD
+0.3V
V
REFIN
. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, V
DD
+0.3V
V
OUT1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DD
, GND
Continuous Current, Any Pin . . . . . . . . -20mA, +20mA
Package Power Dissipation Ratings (T
A
= +70°C)
PDIP (derate 9mW/°C above +70°C) . . . . 117mW
SOIC (derate 6mW/°C above +70°C) . . . 155mW
Operating Temperature Range . . . . . -40°C to + 85°C
Storage Temperature Range . . . . . . -65°C to +165°C
Lead Temperature (soldering, 10 sec) . . . . . . +300°C
Notes
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies.
All inputs have protection diodes
which will protect the device from short
transients outside the supplies of less than 100mA for less than 100
m
s.
Rev. 1.30
5
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