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874328BYI-01LF

Description
Clock Drivers & Distribution 2.5V Differential Clock Divider/Buffer
Categorylogic    logic   
File Size357KB,23 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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874328BYI-01LF Overview

Clock Drivers & Distribution 2.5V Differential Clock Divider/Buffer

874328BYI-01LF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeTQFP
package instruction10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ACD, TQFP-64
Contacts64
Manufacturer packaging codeEDG64P2
Reach Compliance Codecompliant
ECCN codeEAR99
series5V
Input adjustmentSTANDARD
JESD-30 codeS-PQFP-G64
JESD-609 codee3
length10 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level3
Number of functions1
Number of inverted outputs6
Number of terminals64
Actual output times6
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTFQFP
Encapsulate equivalent codeTQFP64,.47SQ
Package shapeSQUARE
Package formFLATPACK
Peak Reflow Temperature (Celsius)260
power supply2.5 V
Prop。Delay @ Nom-Sup4.8 ns
propagation delay (tpd)4.8 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.07 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width10 mm
minfmax650 MHz
Base Number Matches1
2.5V Differential Clock Divider/Buffer
874328I-01
Data Sheet
General Description
The 874328I-01 is a high-performance differential ÷1 and ÷4 clock
divider and fanout buffer. The device is designed for the
frequency-division and signal fanout of high-frequency, low
phase-noise clock signals. The differential input signal is frequency
divided by ÷1 and ÷4. Three LVPECL and three LVDS output banks
are provided with a total of twenty differential outputs. The
874328I-01 is characterized to operate from a 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 874328I-01 ideal for those clock distribution applications
demanding well-defined performance and repeatability.
Features
One differential input LVPECL reference clock
Differential pair can accept the following differential input
levels: LVPECL, LVDS, CML, SSTL
Integrated input termination resistors
One bank of three LVPECL outputs (÷1 frequency-divided)
One bank of three LVPECL outputs (÷4 frequency-divided)
One bank of two LVPECL outputs (÷4 frequency-divided)
Two banks of three LVDS outputs (÷4 frequency-divided)
One bank of six LVDS outputs (÷4 frequency-divided)
Total of twenty differential clock outputs
Maximum input frequency: 650MHz
Maximum output frequency: 650MHz (÷1 outputs)
Maximum output frequency: 162.5MHz (÷4 outputs)
LVCMOS interface levels for all control inputs
Output skew: 70ps (maximum)
Part-to-part skew: 250ps (maximum)
Full 2.5V supply voltage
Available in lead-free (RoHS 6) package
-40°C to 85°C ambient operating temperature
Pin Assignment
QF2
nQF1
QF1
nQF0
QF0
V
CCOF
V
EE
V
CCOF
nQF5
QF5
nQF4
QF4
nQF3
QF3
nQF2
V
EE
V
CCOA
QA0
nQA0
QA1
nQA1
QA2
nQA2
QB0
nQB0
QB1
nQB1
QB2
nQB2
V
CCOB
CLK_EN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
3
46
4
45
ICS874328I-01
5
44
64-Lead TQFP, E-Pad
43
6
7
42
10mm x 10mm x 1.0mm
8
41
package body
9
40
Y package
10
39
Top View
38
11
12
37
13
36
35
14
1
2
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
V
EE
V
CCODE
QE0
nQE0
QE1
nQE1
QE2
nQE2
QD0
nQD0
QD1
nQD1
QD2
nQD2
V
CCODE
V
EE
V
EE
OEF
V
CCOC
nQC1
QC1
nQC0
QC0
OEE
OED
V
CC
OEC
nCLK
V
REF
V
T
CLK
OEB
OEA
Block Diagram
÷1
CLK
nCLK
50
50
f
REF
QA[0:2]
nQA[0:2]
(LVPECL)
÷4
QB[0:2]
V
T
V
REF
CLK_EN
nQB[0:2]
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
(LVPECL)
QC[0:1]
nQC[0:1]
(LVPECL)
QD[0:2]
nQD[0:2]
(LVDS)
©2016 Integrated Device Technology, Inc
1
Revision A January 27, 2016

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874328BYI-01LF 874328BYI-01LFT
Description Clock Drivers & Distribution 2.5V Differential Clock Divider/Buffer Clock Drivers & Distribution 2.5V Differential Clock Divider/Buffer
Brand Name Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Parts packaging code TQFP TQFP
package instruction 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ACD, TQFP-64 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ACD, TQFP-64
Contacts 64 64
Manufacturer packaging code EDG64P2 EDG64P2
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
series 5V 5V
Input adjustment STANDARD STANDARD
JESD-30 code S-PQFP-G64 S-PQFP-G64
JESD-609 code e3 e3
length 10 mm 10 mm
Logic integrated circuit type LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
Humidity sensitivity level 3 3
Number of functions 1 1
Number of inverted outputs 6 6
Number of terminals 64 64
Actual output times 6 6
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TFQFP TFQFP
Encapsulate equivalent code TQFP64,.47SQ TQFP64,.47SQ
Package shape SQUARE SQUARE
Package form FLATPACK FLATPACK
Peak Reflow Temperature (Celsius) 260 260
power supply 2.5 V 2.5 V
Prop。Delay @ Nom-Sup 4.8 ns 4.8 ns
propagation delay (tpd) 4.8 ns 4.8 ns
Certification status Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.07 ns 0.07 ns
Maximum seat height 1.2 mm 1.2 mm
Maximum supply voltage (Vsup) 2.625 V 2.625 V
Minimum supply voltage (Vsup) 2.375 V 2.375 V
Nominal supply voltage (Vsup) 2.5 V 2.5 V
surface mount YES YES
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
Terminal form GULL WING GULL WING
Terminal pitch 0.5 mm 0.5 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature 30 30
width 10 mm 10 mm
minfmax 650 MHz 650 MHz
Base Number Matches 1 1
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