DS2154
Enhanced E1 Single-Chip Transceiver
www.maxim-ic.com
FEATURES
Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality
On-Board Long- and Short-Haul Line
Interface for Clock/Data Recovery and
Waveshaping
32-Bit or 128-Bit Crystal-Less Jitter
Attenuator
Generates Line Build-Outs for Both 120Ω
and 75Ω Lines
Frames to FAS, CAS, and CRC4 Formats
Dual On-Board Two-Frame Elastic Store Slip
Buffers That can Connect to Asynchronous
Backplanes Up to 8.192MHz
8-Bit Parallel Control Port That can be Used
Directly on Either Multiplexed or
Nonmultiplexed Buses (Intel or Motorola)
Extracts and Inserts CAS Signaling
Detects and Generates Remote and AIS
Alarms
Programmable Output Clocks for Fractional
E1, H0, and H12 Applications
Fully Independent Transmit and Receive
Functionality
Full Access to Both Si and Sa Bits Aligned
with CRC Multiframe
Four Separate Loopbacks for Testing
Functions
Large Counters for Bipolar and Code
Violations, CRC4 Codeword Errors, FAS
Errors, and E Bits
Pin Compatible with DS2152 T1 Enhanced
Single-Chip Transceiver
5V Supply; Low-Power CMOS
100-Pin, 14mm
2
LQFP Package
PIN CONFIGURATION
TOP VIEW
DS2154
ORDERING INFORMATION
PART
DS2154L
DS2154L+
DS2154LN
DS2154LN+
TEMP
RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
100 LQFP
100 LQFP
100 LQFP
100 LQFP
+
Denotes lead-free/RoHS-compliant package
.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
100
1
LQFP
(14mm x 14mm)
1 of 87
REV: 011706
DS2154
TABLE OF CONTENTS
1
DETAILED DESCRIPTION....................................................................................................6
1.1
1.1.1
I
NTRODUCTION
............................................................................................................................. 6
New Features......................................................................................................................................... 6
1.2
1.3
F
UNCTIONAL
D
ESCRIPTION
........................................................................................................... 7
R
EADER
’
S
N
OTE
........................................................................................................................... 7
T
RANSMIT
S
IDE
D
IGITAL
P
INS
...................................................................................................... 11
R
ECEIVE
S
IDE
D
IGITAL
P
INS
........................................................................................................ 12
P
ARALLEL
C
ONTROL
P
ORT
P
INS
................................................................................................. 13
L
INE
I
NTERFACE
P
INS
................................................................................................................. 14
S
UPPLY
P
INS
.............................................................................................................................. 14
2
PIN DESCRIPTION................................................................................................................9
2.1
2.2
2.3
2.4
2.5
3
4
PARALLEL PORT ...............................................................................................................20
CONTROL, ID, AND TEST REGISTERS ............................................................................20
4.1
4.2
4.3
4.4
4.5
F
RAMER
L
OOPBACK
.................................................................................................................... 29
L
OCAL
L
OOPBACK
....................................................................................................................... 29
R
EMOTE
L
OOPBACK
.................................................................................................................... 29
P
OWER
-U
P
S
EQUENCE
............................................................................................................... 30
A
UTOMATIC
A
LARM
G
ENERATION
................................................................................................ 30
CRC4 S
YNC
C
OUNTER
............................................................................................................... 33
BPV
OR
C
ODE
V
IOLATION
C
OUNTER
........................................................................................... 39
CRC4 E
RROR
C
OUNTER
............................................................................................................ 40
E-B
IT
C
OUNTER
......................................................................................................................... 40
FAS E
RROR
C
OUNTER
............................................................................................................... 41
5
6
STATUS AND INFORMATION REGISTERS ......................................................................31
5.1
6.1
6.2
6.3
6.4
ERROR COUNT REGISTERS.............................................................................................39
7
8
DS0 MONITORING FUNCTION ..........................................................................................42
SIGNALING OPERATION...................................................................................................46
8.1
8.2
8.2.1
8.2.2
P
ROCESSOR
-B
ASED
S
IGNALING
.................................................................................................. 46
H
ARDWARE
-B
ASED
S
IGNALING
................................................................................................... 49
Receive Side ........................................................................................................................................ 49
Transmit Side ....................................................................................................................................... 49
9
PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK .....................................51
9.1
9.1.1
9.1.2
T
RANSMIT
S
IDE
C
ODE
G
ENERATION
............................................................................................ 51
Simple Idle Code Insertion and Per-Channel Loopback...................................................................... 51
Per-Channel Code Insertion ................................................................................................................ 52
9.2
R
ECEIVE
S
IDE
C
ODE
G
ENERATION
.............................................................................................. 53
10
11
11.1
11.2
CLOCK BLOCKING REGISTERS..................................................................................55
ELASTIC STORES OPERATION ...................................................................................57
R
ECEIVE
S
IDE
............................................................................................................................ 57
T
RANSMIT
S
IDE
.......................................................................................................................... 57
12
12.1
12.2
12.3
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION................................58
H
ARDWARE
S
CHEME
.................................................................................................................. 58
I
NTERNAL
R
EGISTER
S
CHEME
B
ASED ON
D
OUBLE
-F
RAME
........................................................... 58
I
NTERNAL
R
EGISTER
S
CHEME
B
ASED ON
CRC4 M
ULTIFRAME
..................................................... 61
2 of 87
DS2154
13
13.1
13.2
13.3
LINE INTERFACE FUNCTION .......................................................................................63
R
ECEIVE
C
LOCK AND
D
ATA
R
ECOVERY
....................................................................................... 64
T
RANSMIT
W
AVESHAPING AND
L
INE
D
RIVING
............................................................................... 64
J
ITTER
A
TTENUATOR
.................................................................................................................. 65
14
15
16
17
17.1
TIMING DIAGRAMS .......................................................................................................69
DC CHARACTERISTICS................................................................................................76
AC CHARACTERISTICS................................................................................................77
PACKAGE INFORMATION ............................................................................................87
100-P
IN
LQFP (56-G5002-000)................................................................................................. 87
3 of 87
DS2154
LIST OF FIGURES
Figure 1-1. DS2154 Enhanced E1 Single-Chip Transceiver ...................................................................... 8
Figure 13-1. External Analog Connections............................................................................................... 66
Figure 13-2. Jitter Tolerance .................................................................................................................... 67
Figure 13-3. Transmit Waveform Template .............................................................................................. 67
Figure 13-4. Jitter Attenuation .................................................................................................................. 68
Figure 14-1. Receive Side Timing ............................................................................................................ 69
Figure 14-2. Receive Side Boundary Timing (with Elastic Store Disabled) .............................................. 69
Figure 14-3. Receive Side 1.544MHz Boundary Timing (with Elastic Store Enabled) ............................. 70
Figure 14-4. Receive Side 2.048MHz Boundary Timing (with Elastic Store Enabled) ............................. 70
Figure 14-5. Transmit Side Timing ........................................................................................................... 71
Figure 14-6. Transmit Side Boundary Timing ........................................................................................... 71
Figure 14-7. Transmit Side 1.544MHz Boundary Timing (with Elastic Store Enabled) ............................ 72
Figure 14-8. Transmit Side 2.048MHz Boundary Timing (with Elastic Store Enabled) ............................ 72
Figure 14-9. G.802 Timing........................................................................................................................ 73
Figure 14-10. Synchronization Flow Chart ............................................................................................... 74
Figure 14-11. Transmit Data Flow ............................................................................................................ 75
Figure 16-1. Intel Bus Read AC Timing (BTS = 0/MUX = 1) .................................................................... 77
Figure 16-2. Intel Bus Write AC Timing (BTS = 0/MUX = 1)..................................................................... 78
Figure 16-3. Motorola Bus AC Timing (BTS = 1/MUX = 1)....................................................................... 78
Figure 16-4. Receive Side AC Timing ...................................................................................................... 80
Figure 16-5. Receive System Side AC Timing ......................................................................................... 81
Figure 16-6. Receive Line Interface AC Timing........................................................................................ 81
Figure 16-7. Transmit Side AC Timing ..................................................................................................... 83
Figure 16-8. Transmit System Side AC Timing ........................................................................................ 84
Figure 16-9. Transmit Line Interface Side AC Timing............................................................................... 84
Figure 16-10. Intel Bus Read AC Timing (BTS = 0/MUX = 0) .................................................................. 85
Figure 16-11. Intel Bus Write AC Timing (BTS=0/MUX=0)....................................................................... 86
Figure 16-12. Motorola Bus Read AC Timing (BTS = 1/MUX = 0) ........................................................... 86
Figure 16-13. Motorola Bus Write AC Timing (BTS = 1/MUX = 0) ........................................................... 86
4 of 87
DS2154
LIST OF TABLES
Table 2-1. Register Map ........................................................................................................................... 15
Table 4-1. Sync/Resync Criteria............................................................................................................... 21
Table 5-1. Alarm Criteria .......................................................................................................................... 35
Table 13-1. Line Build-Out Select in LICR................................................................................................ 64
Table 13-2. Transformer Specifications.................................................................................................... 65
Table 15-1. Recommended DC Operating Conditions ............................................................................. 76
Table 15-2. Capacitance .......................................................................................................................... 76
Table 15-3. DC Characteristics ................................................................................................................ 76
Table 16-1. AC Characteristics—Multiplexed Parallel Port (MUX = 1)..................................................... 77
Table 16-2. AC Characteristics—Receive Side ........................................................................................ 79
Table 16-3. AC Characteristics—Transmit Side ....................................................................................... 82
Table 16-4. AC Characteristics—Nonmultiplexed Parallel Port (MUX = 0) .............................................. 85
5 of 87
京公网安备 11010802033920号
EEWORLD
