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Stratix IV Device Handbook
Volume 1
January 2016
Feedback Subscribe
1–2
Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
Feature Summary
The following list summarizes the Stratix IV device family features:
■
Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices
supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively
Dedicated circuitry to support physical layer functionality for popular serial
protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE),
Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre
Channel, SFI-5, and Interlaken
Complete PCIe protocol solution with embedded PCIe hard IP blocks that
implement PHY-MAC layer, Data Link layer, and Transaction layer functionality
f
For more information, refer to the
IP Compiler for PCI Express User Guide.
■
■
■
Programmable transmitter pre-emphasis and receiver equalization circuitry to
compensate for frequency-dependent losses in the physical medium
Typical physical medium attachment (PMA) power consumption of 100 mW at
3.125 Gbps and 135 mW at 6.375 Gbps per channel
72,600 to 813,050 equivalent LEs per device
7,370 to 33,294 Kb of enhanced TriMatrix memory consisting of three RAM block
sizes to implement true dual-port memory and FIFO buffers
High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit,
12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz
Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery
clocks (PCLK) per device
Programmable power technology that minimizes power while maximizing device
performance
Up to 1,120 user I/O pins arranged in 24 modular I/O banks that support a wide
range of single-ended and differential I/O standards
Support for high-speed external memory interfaces including DDR, DDR2,
DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular
I/O banks
High-speed LVDS I/O support with serializer/deserializer (SERDES), dynamic
phase alignment (DPA), and soft-CDR circuitry at data rates up to 1.6 Gbps
Support for source-synchronous bus standards, including SGMII, GbE, SPI-4
Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
Pinouts for Stratix IV E devices designed to allow migration of designs from
Stratix III to Stratix IV E with minimal PCB impact
■
■
■
■
■
■
■
■
■
■
■
Stratix IV Device Handbook
Volume 1
January 2016 Altera Corporation
Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
1–3
Stratix IV GX Devices
Stratix IV GX devices provide up to 48 full-duplex CDR-based transceiver channels
per device:
■
Thirty-two out of the 48 transceiver channels have dedicated physical coding
sublayer (PCS) and physical medium attachment (PMA) circuitry and support
data rates between 600 Mbps and 8.5 Gbps
The remaining 16 transceiver channels have dedicated PMA-only circuitry and
support data rates between 600 Mbps and 6.5 Gbps
■
1
The actual number of transceiver channels per device varies with device selection. For
more information about the exact transceiver count in each device, refer to
Table 1–1
on page 1–11.
For more information about transceiver architecture, refer to the
Transceiver
Architecture in Stratix IV Devices
chapter.
Figure 1–1
shows a high-level Stratix IV GX chip view.
Figure 1–1. Stratix IV GX Chip View
(1)
General Purpose
I/O and Memory
Interface
Transceiver Transceiver Transceiver Transceiver
Block
Block
Block
Block
PLL
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PCI Express
Hard IP Block
General Purpose
I/O and Memory
Interface
PLL
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PCI Express
Hard IP Block
PCI Express
Hard IP Block
Transceiver Transceiver Transceiver Transceiver
Block
Block
Block
Block
1
PLL
PLL
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
PLL
PLL
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PCI Express
Hard IP Block
PLL
PLL
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PLL
General Purpose
I/O and Memory
Interface
PLL
General Purpose
I/O and Memory
Interface
PLL
PLL
Transceiver Block
General Purpose I/O and
High-Speed LVDS I/O
with DPA and Soft CDR
600 Mbps-8.5 Gbps CDR-based Transceiver
General Purpose I/O and 150 Mbps-1.6 Gbps
LVDS interface with DPA and Soft-CDR
Note to
Figure 1–1:
(1) Resource counts vary with device selection, package selection, or both.
January 2016
Altera Corporation
Stratix IV Device Handbook
Volume 1
1–4
Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
Stratix IV E Device
Stratix IV E devices provide an excellent solution for applications that do not require
high-speed CDR-based transceivers, but are logic, user I/O, or memory intensive.
Figure 1–2
shows a high-level Stratix IV E chip view.
Figure 1–2. Stratix IV E Chip View
(1)
General Purpose
I/O and Memory PLL
Interface
PLL
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
PLL
General Purpose
I/O and Memory
Interface
PLL
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
PLL
PLL
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
PLL
PLL
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
PLL
General Purpose
I/O and Memory PLL
Interface
General Purpose
I/O and Memory
Interface
PLL
PLL
General Purpose I/O and
High-Speed LVDS I/O with DPA
and Soft-CDR
General Purpose I/O and
150 Mbps-1.6 Gbps
LVDS interface with DPA and Soft-CDR
Note to
Figure 1–2:
(1) Resource counts vary with device selection, package selection, or both.
Stratix IV Device Handbook
Volume 1
January 2016 Altera Corporation
Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
1–5
Stratix IV GT Devices
Stratix IV GT devices provide up to 48 CDR-based transceiver channels per device:
■
Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA
circuitry and support data rates between 600 Mbps and 11.3 Gbps
The remaining 16 transceiver channels have dedicated PMA-only circuitry and
support data rates between 600 Mbps and 6.5 Gbps
■
1
The actual number of transceiver channels per device varies with device selection. For
more information about the exact transceiver count in each device, refer to
Table 1–7
on page 1–16.
For more information about Stratix IV GT devices and transceiver architecture, refer
to the
Transceiver Architecture in Stratix IV Devices
chapter.
Figure 1–3
shows a high-level Stratix IV GT chip view.
Figure 1–3. Stratix IV GT Chip View
(1)
1
General Purpose
I/O and Memory
Interface
Transceiver Transceiver
Block
Block
PLL
PLL
General Purpose
I/O and Memory
Interface
PLL
General Purpose
I/O and
High-Speed
LVDS I/O
with
DPA and Soft CDR
PCI Express
Hard IP Block
PCI Express
Hard IP Block
Transceiver Transceiver
Block
Block
Transceiver Transceiver
Block
Block
PLL
General Purpose
I/O and
High-Speed
LVDS I/O
with
DPA and Soft CDR
PCI Express
Hard IP Block
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock
Networks)
PLL
PLL
General Purpose
I/O and
High-Speed
LVDS I/O
with
DPA and Soft CDR
PCI Express
Hard IP Block
PLL
PLL
General Purpose
I/O and
High-Speed
LVDS I/O
with
DPA and Soft CDR
Transceiver Transceiver
Block
Block
PLL
General Purpose
I/O and Memory
Interface
PLL
General Purpose
I/O and Memory
Interface
PLL
PLL
Transceiver Block
General Purpose I/O and
High-Speed LVDS I/O
with
DPA and Soft CDR
600 Mbps-11.3 Gbps CDR-based Transceiver
General Purpose I/O and
up
to 1.6 Gbps
LVDS interface
with
DPA and Soft-CDR
Note to
Figure 1–3:
(1) Resource counts vary with device selection, package selection, or both.
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ADI Reference Circuit
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