Changes to Figure 1 .......................................................................... 1
Changes to Ordering Guide .......................................................... 20
2/15—Revision 0: Initial Version
Rev. A | Page 2 of 20
Data Sheet
SPECIFICATIONS
AD7402
V
DD1
= 4.5 V to 5.5 V, V
DD2
= 3 V to 5.5 V, V
IN
+ = −250 mV to +250 mV, V
IN
− = 0 V, T
A
= −40°C to +105°C, tested with sinc3 filter, 256
decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective ground.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution
Integral Nonlinearity (INL)
1
Differential Nonlinearity (DNL)
1
Offset Error
1
Offset Drift vs. Temperature
Offset Drift vs. V
DD1
Gain Error
1
Gain Error Drift vs. Temperature
Gain Error Drift vs. V
DD1
ANALOG INPUT
Input Voltage Range
Input Common-Mode Voltage Range
Dynamic Input Current
Input Capacitance
DYNAMIC SPECIFICATIONS
Signal-to-(Noise + Distortion) Ratio (SINAD)
1
Signal-to-Noise Ratio (SNR)
1
Total Harmonic Distortion (THD)
1
Peak Harmonic or Spurious Noise (SFDR)
1
Effective Number of Bits (ENOB)
1
Noise Free Code Resolution
1
ISOLATION TRANSIENT IMMUNITY
1
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
POWER REQUIREMENTS
V
DD1
V
DD2
I
DD1
I
DD2
POWER DISSIPATION
1
Min
16
Typ
Max
Unit
Bits
LSB
LSB
mV
µV/°C
µV/V
% FSR
ppm/°C
µV/°C
mV/V
mV
µA
µA
pF
dB
dB
dB
dB
Bits
Bits
kV/µs
V
V
V
V
mA
mA
mA
mW
Test Conditions/Comments
Filter output truncated to 16 bits
Guaranteed no missed codes to 16 bits
±1
±0.2
1.7
85
0.2
18
11
0.2
−320
−200 to +300
±19
0.05
14
74
86
82
87
−84
−84
13.5
30
±5
±0.99
±0.75
5
±0.5
32
20
+320
±28
V
IN
+ = ±250 mV, V
IN
− = 0 V
V
IN
+ = 0 V, V
IN
− = 0 V
V
IN
+ = 35 Hz
12
14
25
V
DD2
− 0.1
0.4
4.5
3
26
6
4.5
5.5
5.5
31
7
5.5
209
I
O
= −200 µA
I
O
= +200 µA
V
DD1
= 5.5 V
V
DD2
= 5.5 V
V
DD2
= 3.3 V
V
DD1
= V
DD2
= 5.5 V
See the Terminology section.
Rev. A | Page 3 of 20
AD7402
TIMING SPECIFICATIONS
V
DD1
= 4.5 V to 5.5 V, V
DD2
= 3 V to 5.5 V, T
A
= −40°C to +105°C, unless otherwise noted.
Table 2.
Parameter
1
f
MCLKOUT2
t
13
t
23
t
3
t
4
1
2
Data Sheet
Min
9.4
44
33
33
Typ
10
Max
10.6
±10
Unit
MHz
ns
ns
ns
ns
Description
Master clock output frequency
Data access time after MCLKOUT rising edge
Data hold time after MCLKOUT falling edge
Master clock low time
Master clock high time
Sample tested during initial release to ensure compliance.
Mark space ratio for clock output is 45/55 to 55/45.
3
Defined as the time required for the output to cross 0.8 V or 2.0 V for VDD2 = 3 V to 3.6 V, or when the output crosses 0.8 V or 0.7 × VDD2 for VDD2 = 4.5 V to 5.5 V, as
outlined in Figure 2. Measured with a ±200 μA load and a 25 pF load capacitance.
t
4
MCLKOUT
2.0V OR 0.7V × V
DD2 1
0.8V
t
1
MDAT
t
2
t
3
2.0V OR 0.7V × V
DD2 1
0.8V
12898-002
1
SEE NOTE 3 OF TABLE 2 FOR FURTHER DETAILS.
Figure 2. Data Timing
Rev. A | Page 4 of 20
Data Sheet
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Resistance (Input to Output)
1
Capacitance (Input to Output)
1
IC Junction to Ambient Thermal Resistance
1
AD7402
Symbol
R
I-O
C
I-O
θ
JA
Min
Typ
10
12
2.2
105
Max
Unit
Ω
pF
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces
The device is considered a 2-terminal device: Pin 1 to Pin 4 are shorted together, and Pin 5 to Pin 8 are shorted together.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter
Input-to-Output Momentary Withstand Voltage
Minimum External Air Gap (Clearance)
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
1
2
Symbol
V
ISO
L(I01)
L(I02)
Value
5000 min
8.1 min
1, 2
8.1 min
1
0.034 min
>400
II
Unit
V
mm
mm
mm
V
CTI
Test Conditions/Comments
1-minute duration
Measured from input terminals to output
terminals, shortest distance through air
Measured from input terminals to output
terminals, shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table I)
In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 meters.
Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained.
REGULATORY INFORMATION
Table 5.
UL
1
Recognized under 1577
Component Recognition
Program
1
5000 V rms Isolation Voltage
Single Protection
CSA
Approved under CSA Component Acceptance Notice 5A
Basic insulation per CSA 60950-1-07 and IEC 60950-1,
810 V rms (1145 V
PEAK
) maximum working voltage
3
Reinforced insulation per CSA 60950-1-07 and
IEC 60950-1, 405 V rms (583 V
PEAK
) maximum working
voltage
3
Reinforced insulation per IEC 60601-1, 250 V rms
(353 V
PEAK
) maximum working voltage
File 205078
VDE
2
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
2
Reinforced insulation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12, 1250 V
PEAK
File E214100
1
2
File 2471900-4880-0001
In accordance with UL 1577, each AD7402-8 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA).
In accordance with DIN V VDE V 0884-10, each AD7402-8 is proof tested by applying an insulation test voltage ≥ 2344 V
PEAK
for 1 second (partial discharge detection limit = 5 pC).
3
Rating is calculated for a pollution degree of 2 and a Material Group III. The
AD7402
RI-8-1 package material is rated by CSA to a CTI of >400 V and therefore
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