MC14504B
Hex Level Shifter for TTL to
CMOS or CMOS to CMOS
The MC14504B is a hex non−inverting level shifter using CMOS
technology. The level shifter will shift a TTL signal to CMOS logic
levels for any CMOS supply voltage between 5 and 15 volts. A control
input also allows interface from CMOS to CMOS at one logic level to
another logic level: Either up or down level translating is
accomplished by selection of power supply levels V
DD
and V
CC
.
The V
CC
level sets the input signal levels while V
DD
selects the output
voltage levels.
Features
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•
UP Translates from a Low to a High Voltage or DOWN Translates
•
•
•
•
•
•
•
from a High to a Low Voltage
Input Threshold Can Be Shifted for TTL Compatibility
No Sequencing Required on Power Supplies or Inputs for Power Up
or Power Down
3 to 18 Vdc Operation for V
DD
and V
CC
Diode Protected Inputs to V
SS
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
SOIC−16
D SUFFIX
CASE 751B
SOEIAJ−16
F SUFFIX
CASE 966
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
V
CC
A
out
A
in
B
out
B
in
C
out
C
in
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
F
out
F
in
MODE
E
out
E
in
D
out
D
in
MARKING DIAGRAMS
16
14504BG
AWLYWW
16
MC14504B
ALYWG
1
SOEIAJ−16
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
CC
V
DD
V
in
V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
DC Supply Voltage Range
Input Voltage Range
(DC or Transient)
Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to +18.0
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±10
500
−55 to +125
−65 to +150
260
Unit
V
V
V
V
mA
mW
°C
°C
°C
1
SOIC−16
16
14
504B
ALYWG
G
1
TSSOP−16
A
WL, L
YY, Y
WW, W
G or
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
(Note: Microdot may be in either location)
ORDERING INFORMATION
Stresses exceeding those listed in the Maximum Ratings table may damage the
See detailed ordering and shipping information in the package
device. If any of these limits are exceeded, device functionality should not be
dimensions section on page 2 of this data sheet.
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V
in
and V
out
should be constrained to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V
SS
or V
DD
). Unused outputs must be left open.
©
Semiconductor Components Industries, LLC, 2014
1
July, 2014 − Rev. 9
Publication Order Number:
MC14504B/D
MC14504B
SWITCHING CHARACTERISTICS
(C
L
= 50 pF, T
A
= 25_C)
Characteristic
Propagation Delay, High to Low
Symbol
t
PHL
Shifting Mode
TTL – CMOS
V
DD
> V
CC
CMOS – CMOS
V
DD
> V
CC
CMOS – CMOS
V
CC
> V
DD
Propagation Delay, Low to High
t
PLH
TTL – CMOS
V
DD
> V
CC
CMOS – CMOS
V
DD
> V
CC
CMOS – CMOS
V
CC
> V
DD
Output Rise and Fall Time
t
TLH
, t
THL
ALL
V
CC
Vdc
5.0
5.0
5.0
5.0
10
10
15
15
5.0
5.0
5.0
5.0
10
10
15
15
−
−
−
V
DD
Vdc
10
15
10
15
15
5.0
5.0
10
10
15
10
15
15
5.0
5.0
10
5.0
10
15
Min
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Limits
Typ
(Note 3)
140
140
120
120
70
185
185
175
170
160
170
170
100
275
275
145
100
50
40
Max
280
280
240
240
140
370
370
350
340
320
340
340
200
550
550
290
200
100
80
Unit
ns
ns
ns
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
7
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)
6
5
4
3
2
1
0
0
5
10
15
V
DD
, SUPPLY VOLTAGE (Vdc)
20
V
CC
= 5 V
V
CC
= 10 V
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)
7
6
5
4
3
2
1
0
0
5
10
15
V
DD
, SUPPLY VOLTAGE (Vdc)
20
V
CC
= 5 V
Figure 1. Input Switchpoint CMOS to CMOS Mode
20
Figure 2. Input Switchpoint TTL to CMOS Mode
20
VDD, SUPPLY VOLTAGE (Vdc)
10
VDD, SUPPLY VOLTAGE (Vdc)
15
15
10
5
5
0
0
0
20
0
5
10
15
V
CC
, SUPPLY VOLTAGE (Vdc)
20
5
10
15
V
CC
, SUPPLY VOLTAGE (Vdc)
Figure 3. Operating Boundary CMOS to CMOS Mode
Figure 4. Operating Boundary TTL to CMOS Mode
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4
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
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MC14504B
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F
ISSUE B
16X
K
REF
0.10 (0.004)
0.15 (0.006) T U
S
M
T U
S
V
S
K
2X
L/2
16
9
J1
B
−U−
SECTION N−N
J
N
L
PIN 1
IDENT.
1
8
0.15 (0.006) T U
S
A
−V−
N
F
DETAIL E
−W−
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
C
0.10 (0.004)
−T−
SEATING
PLANE
H
D
G
DETAIL E
SOLDERING FOOTPRINT
7.06
1
16X
0.36
16X
1.26
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5
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÇÇÇ
0.25 (0.010)
M
K1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
_
8
_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0
_
8
_
0.65
PITCH
DIMENSIONS: MILLIMETERS
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