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840N202CKI-000LF

Description
Clock Synthesizer / Jitter Cleaner FemtoClock NG UFT
Categorysemiconductor    Analog mixed-signal IC   
File Size480KB,31 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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840N202CKI-000LF Overview

Clock Synthesizer / Jitter Cleaner FemtoClock NG UFT

840N202CKI-000LF Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerIDT (Integrated Device Technology)
Product CategoryClock Synthesizer / Jitter Cleaner
RoHSDetails
Package / CaseVFQFPN-40
PackagingTray
Height0.9 mm
Length6 mm
Width6 mm
Moisture SensitiveYes
Factory Pack Quantity490
FemtoClock® NG Universal Frequency
Translator
ICS840N202I
DATA SHEET
General Description
The ICS840N202I is a highly flexible FemtoClock® NG general
purpose, low phase noise Frequency Translator / Synthesizer with
alarm and monitoring functions suitable for networking and
communications applications. It is able to generate any output
frequency in the 1MHz - 250MHz range (see Table 3 for details). A
wide range of input reference clocks and a range of low-cost
fundamental mode crystal frequencies may be used as the source
for the output frequency.
The ICS840N202I has three operating modes to support a very
broad spectrum of applications:
1) Frequency Synthesizer
Features
Fourth generation FemtoClock® NG technology
Universal Frequency Translator/Frequency Synthesizer
Two LVCMOS/LVTTL outputs
Both outputs may be set to use 2.5V or 3.3V output levels
Programmable output frequency: 1.0MHz to 250MHz
Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, HCSL
Input frequency range: 8kHz - 710MHz
Crystal input frequency range: 16MHz - 40MHz
Two factory-set register configurations for power-up default state
Synthesizes output frequencies from a 16MHz - 40MHz
fundamental mode crystal.
Fractional feedback division is used, so there are no
requirements for any specific crystal frequency to produce the
desired output frequency with a high degree of accuracy.
Power-up default configuration pin or register selectable
Configurations customized via One-Time Programmable ROM
Settings may be overwritten after power-up via I
2
C
I
2
C Serial interface for register programming
2) High-Bandwidth Frequency Translator
Applications: PCI Express, Computing, General Purpose
Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation, so it will not attenuate much jitter on the input
reference.
Applications: Networking & Communications.
Translates any input clock in the 8kHz - 710MHz frequency
range into any supported output frequency.
This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external crystal to provide
significant jitter attenuation.
RMS phase jitter at 125MHz, using a 40MHz crystal
(12kHz - 20MHz): 616fs (typical), Low Bandwidth Mode (FracN)
Output supply voltage modes:
V
DD
/V
DDA
/V
DDO
3.3V/3.3V/3.3V
3.3V/3.3V/2.5V
2.5V/2.5V/2.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
3) Low-Bandwidth Frequency Translator
Pin Assignment
CLK_ACTIVE
XTALBAD
CLK1BAD
HOLDOVER
CLK0BAD
GND
V
DDA
This device provides two factory-programmed default power-up
configurations burned into One-Time Programmable (OTP) memory.
The configuration to be used is selected by the CONFIG pin. The two
configurations are specified by the customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices. The two configurations may be completely independent of
one another.
One usage example might be to install the device on a line card with
two optional daughter cards: an OC-3 option (configuration 0)
requiring a 155.52MHz clock translated from a 19.44MHz input and
a Gigabit Ethernet option (configuration 1) requiring a 125MHz clock
translated from the same 19.44MHz input reference.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I
2
C interface and the
device can be completely reconfigured. However, these settings
would have to be re-written each time the device powers-up.
LF1
LF0
XTAL_IN
XTAL_OUT
V
DD
CLK_SEL
CLK0
nCLK0
V
DD
GND
CLK1
nCLK1
1
2
3
4
5
6
7
8
9
10
40 39 38 37 36 35 34 33 32 31
30
29
nc
LOCK_IND
V
DD
OE0
GND
Q0
V
DDO
Q1
GND
OE1
GND
ICS840N202I
40 Lead VFQFN
6mm x 6mm x 0.925mm
K Package
Top View
28
27
26
25
24
23
22
21
11 12 13 14 15 16 17 18 19 20
CONFIG
S_A1
S_A0
Rsvd
PLL_BYPASS
SDATA
SCLK
Rsvd
V
DD
nc
ICS840N202CKI REVISION A NOVEMBER 1, 2013
1
©2013 Integrated Device Technology, Inc.

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