NJU26060-05A
Digital Signal Processor with PWM Modulator
for Correction of Sound
General Description
The NJU26060-05A is a high performance 24-bit digital signal
processor included sampling rate converter (SRC), PWM
modulators. The NJU26060-05A provides Stereo Expander II,
Elevation, 256Tap FIR filter, 8band IIR filter, Dynamic Bass Boost,
two systems Limiter, and Dynamic Range Compression.
The NJU26060-05A is suitable for TV, mini component,
CD radio-cassette, speakers system and other audio products.
Package
NJU26060V-05A
Features
- Hardware
24bit Fixed-point Digital Signal Processing
Clock Frequency
: 24.576MHz, Embedded PLL Circuit
Sampling rate converter (SRC) : Fs=8kHz to 192kHz
→
48kHz
PWM modulator
: 4ch Outputs (2 stereos)
Digital interface transmitter (DIT) : 1 port
Digital Audio Interface
: 3 Input ports / 2 Output ports (switch over from PWM output)
Digital Audio Format
: I
2
S 24bit, Left-justified, Right-justified, BCK : 32/64fs
Master / Slave Mode
- Sampling Rate Converter: Slave mode
- DSP: Master Mode
Host Interface
: I
2
C Bus ( Fast-mode/400kbps)
Power Supply
: V
DD
= 3.3V
Input terminal:
: 5V Input tolerant
Package
: SSOP44 (Pb-Free)
- Software
HPF
Input Signal Detect
Input Trim
Stereo ExpanderⅡ
Elevation
256Taps FIR Filter
8Band IIR Filter (7、8Band PEQ + Shelf Filter)
Master Volume
DBB
Xover (HPF/LPF)
DRC
SDO0 DRC Mixer
SDO1 Cch : C/SW Mixer
Delay
Output Trimmer / Inverter
Limiter
BEEP
* The detail hardware specification of the NJU26060-05A is described in the
“NJU26060
Series Hardware
Specification”.
Ver.2014.02.04
-1-
NJU26060-05A
DSP Block Diagram
24Bit Fixed-point DSP Core
BCKO
LRO
SDI0
SDI1
SDI2
Serial Audio
Interface
(Master)
Over Sampling
Digital Filter
Over Sampling
Digital Filter
PWM Modulator 0
Delta-Sigma
Modulator
Delta-Sigma
Modulator
PWM
Generator
PWM
Generator
OUTLP0
OUTLN0
OUTRP0
OUTRN0
PWMEN0
SDI
Select
PWM_MUTEb
PWM_DISb
PWM_ERRb
BCKO
LRO
512fs
BCKI
LRI
SCL
I
2
C INTERFACE
SDA
Sampling Rate
Convertor
(Slave)
PROGRAM
CONTROL
24Bit x 24Bit
MULTIPLIER
ALU
PWM Modulator 1
Over Sampling
Digital Filter
Delta-Sigma
Modulator
PWM
Generator
SDO0
Over Sampling
Digital Filter
Delta-Sigma
Modulator
PWM
Generator
SDO1
PWMEN1
OUTRP1
OUTRN1
OUTLP1
OUTLN1
ADDRESS GENERATION UNIT
RESETb
BCKO
LRO
MCKO
CLKOUT
TIMING
GENERATOR /
PLL
2048fs
256fs
512fs
S/PDIF
Transmitter
OFF
SDO
GPO
CLK
GPIO
INTERFACE
WDC
PROC
FIRMWARE
OTP
PROGRAM
RAM
1.8V
DATA RAM0
DATA RAM1
LDO
VREGO
Fig 1. NJU26060-05A Hardware Block Diagram
Function Block Diagram
SDI0
SDI1
SDI2
HPF
Input Signal
Detect
Input Trim
Stereo
Expander
Ⅱ
Elevation
256Taps
FIR Filter
8Band
IIR Filter
Master
Volume
DBB
BEEP
HPF out
HPF
DRC
DRC Mixer
Limiter
SDO1
(C/SW or SW)
Limiter
SDO0
(L/R)
Output Trimmer
-96dB
~
+24dB
/ Inverter
LPF
DRC
LPF out
C/SW Mixer
Delay
Fig 2. NJU26060-05A Block Diagram
-2-
Ver.2014.02.04
NJU26060-05A
Pin Configuration
RESETb
PWM_MUTEb
PWM_DISb
SDA
SCL
LRI
BCKI
SDI0
SDI1
SDI2
REGDISb
VDD
VSS
VREGO
VDDPLL
VSSPLL
PWMEN1
OUTRN1
OUTRP1
OUTLN1
OUTLP1
VSSPWM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
BCKO
LRO
MCKO
SDO
TEST3
GPO
WDC
PROC
TEST2
CLK
CLKOUT
VDD
VSS
VREGO
TEST1
PWM_ERRb
PWMEN0
OUTRN0
OUTRP0
OUTLN0
OUTLP0
VDDPWM
NJU26060-05A
34
33
32
31
30
29
28
27
26
25
24
23
Fig 3. NJU26060-05A Pin Configuration
Ver.2014.02.04
-3-
NJU26060-05A
Pin Description
Pin Description
Symbol
RESETb
PWM_MUTEb
PWM_DISb
SDA
SCL
LRI
BCKI
SDI0
SDI1
SDI2
REGDISb
VDD
VSS
VREGO
VDDPLL
VSSPLL
PWMEN1
OUTRN1
OUTRP1
OUTLN1
OUTLP1
VSSPWM
VDDPWM
OUTLP0
OUTLN0
OUTRP0
OUTRN0
PWMEN0
PWM_ERRb
TEST1
VREGO
VSS
VDD
CLKOUT
CLK
TEST2
PROC
WDC
GPO
TEST3
SDO
MCKO
LRO
BCKO
I/O
I
I+
I+
OD
I
I-
I-
I-
I-
I-
I
P
G
PI
PA
GA
O
OP
OP
OP
OP
GP
PP
OP
OP
OP
OP
O
I+
I
PI
G
P
O
I
I-
I+
O+
OD
I-
O
O
O
O
Reset
PWM Block Mute request input
PWM Block Standby request input
I
2
C serial data I/O (connect to VSS with 3.3kohm when this is not used)
I
2
C clock (connect to VSS when this is not used)
LR Clock Input for Fs conversion side
Bit Clock Input for Fs conversion side
Audio Data Input 0
Audio Data Input 1
Audio Data Input 2
Built-in Power Supply Enable (connect to VDD)
Power Supply +3.3V
GND
Built-in Power Supply Bypass (connect capacitors 10uF and 0.01uF)
PLL Power Supply +1.8V (connect to VREGO)
PLL Power Supply GND
PWM1 enable output (PWMEN1=’1’: enable)
PWM1 R- output / Audio Data output 1 (setting Firmware)
PWM1 R+ output
PWM1 L- output / Audio Data output 0 (setting Firmware)
PWM1 L+ output
PWM Power Supply GND
PWM Power Supply +3.3V (decoupling capacitor is required to stable power supply)
PWM0 L+ output
PWM0 L- output
PWM0 R+ output
PWM0 R- output
PWM0 enable output (PWMEN0=’1’: enable)
PWM block stop request input (PWM_ERRb=’0’: PWM stop)
for Test (connected to VSS)
Built-in Power Supply Bypass (connect capacitors 10uF and 0.01uF)
GND
Power Supply +3.3V
OSC Output
OSC Clock Input
for Test (connected to VSS)
PROC terminal
Watch dog clock terminal
Signal detection terminal
for Test (connected to VSS)
OFF / DIT output 0 / GPO(same function as pin#39) (selected by command)
Master Clock Output for A/D, D/A
LR clock Output
Bit clock Output
Description
(RESETb=“Low” : DSP Reset)
Table 1.
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Note :
I
I+
OD
I/O
OP
: Input
O: Output
: Input (Pull-up)
I -: Input (Pull-down)
: Bi-directional (Open Drain) This pin requires a pull-up resistance.
: Bi-directional
PI: Built-in Power Supply Bypass
: PWM output(supply for VDDPWM)
NOTICE:
Does not keep the terminal without the pull-up resistance or the pull-down resistance open.
The functions of SDIO0 to SDIO2, SDO, OUTxxx depend on the IC specifications.
-4-
Ver.2014.02.04
NJU26060-05A
Audio Clock
Three kinds of clocks are needed for digital audio data transfer.
(1) LR clock (LRI, LRO) is needed by serial-data transmission. It is the same as the sampling
frequency of a digital audio signal.
(2) Bit clock (BCKI, BCKO) is needed by serial-data transmission. It becomes the multiple of LR
clock.
(3) Master clock (MCKO) needed by A/D, D/A converter, etc. It becomes the multiple of LR clock. It is
not related to serial audio data transmission.
The NJU26060-05A support serial data format that includes 32(32fs) or 64(64fs) BCK clocks.
The NJU26060-05A supplies the clock necessary for digital audio data transmission to an external
device as a master device by each terminal of MCKO, BCKO, and LRO. On the other hand, the sampling
rate converter that works as a slave device takes digital audio data with the clock input to BCKI and the
terminal LRI, and converts the sampling frequency into the clock system composed of
MCKO/BCKO/LRO. After internal reset ends as a master clock, the terminal MCKO sets the buffer
output or 2 dividing frequency the output of the input clock to the terminal CLK. The stop is also possible
according to the command of the firmware.
The NJU26060-05A is used by 512 times the internal operation sampling frequency (It is 24.576MHz
in the sampling frequency 48kHz). In that case, NJU26060-05A can output 64 times, 32 times the bit
clock to of the LR clock one time the sampling frequency and of each, and 512 times and 256 times the
master clock as a mastering device. Table 5 shows the relation of each clock.
The NJU26060 series support two clock frequencies (24.576kHz ,or 22.572kHz) as hardware
specifications. However NJU26060-05A acceptable one clock frequency (24.576kHz), cause of the
software on NJU26060-05A supports one clock frequency (24.576kHz).
Supply Clock for CLK pin Frequency and BCKO,LRO,MCKO
Clock Frequency
Clock Signal
Multiple Frequency
24.576MHz
(for pin#35)
LRO
BCKO(32Fs)
BCKO(64Fs)*
MCKO(256Fs)*
MCKO(512Fs)
1Fs
32Fs
64Fs
256Fs
512Fs
48kHz
1.536MHz
3.072MHz
12.288MHz
24.576MHz
* default for starting up
Table 2.
Serial Audio Data Input/Output
Audio interface of the NJU26060-05A includes three data input ports: SDI0, SDI1 and SDI2 (Table 3),
and three data output ports: SDO0, SDO1 and SDO2 (Table 4).
Table 3.
Pin No.
8
9
10
Serial Audio Input Pin Description
Symbol
Description
SDI0
Audio Data Input 0
SDI1
Audio Data Input 1
SDI2
Audio Data Input 2
Table 4. Serial Audio Output Pin Description
Pin No.
Symbol
Description
20
OUTLN1
Audio Data Output 0 (L/R)
18
OUTRN1
Audio Data Output 1 (C/SW)
41
SDO
OFF
Pin#20, 18 can be change the function to PWM1 output. Pin#41 can be change the function to DIT
(output 0) or GPO output (the function is same as Pin#39). Refer to table1.
Ver.2014.02.04
-5-
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