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8741004AGLFT

Description
Clock Synthesizer / Jitter Cleaner LVDS/HCSL PCIe Jitter Attenuator
Categorylogic    logic   
File Size397KB,19 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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8741004AGLFT Overview

Clock Synthesizer / Jitter Cleaner LVDS/HCSL PCIe Jitter Attenuator

8741004AGLFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP-24
Contacts24
Manufacturer packaging codePGG24
Reach Compliance Codecompliant
ECCN codeEAR99
series8741004
Input adjustmentDIFFERENTIAL
JESD-30 codeR-PDSO-G24
JESD-609 codee3
length7.8 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals24
Actual output times4
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP24,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
minfmax98 MHz
Base Number Matches1
Differential-to-LVDS/0.7V Differential PCI
Express™ Jitter Attenuator
8741004
DATA SHEET
General Description
The 8741004 is a high performance Differential-to-LVDS/0.7V
Differential Jitter Attenuator designed for use in PCI Express™
systems. In some PCI Express systems, such as those found in
desktop PCs, the PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In these
systems, a jitter attenuator may be required to attenuate high
frequency random and deterministic jitter components from the PLL
synthesizer and from the system board. The 8741004 has 3 PLL
bandwidth modes: 200kHz, 600kHz and 2MHz. The 200kHz mode
will provide maximum jitter attenuation, but with higher PLL tracking
skew and spread spectrum modulation from the motherboard
synthesizer may be attenuated. The 600kHz provides an
intermediate bandwidth that can easily track triangular spread
profiles, while providing good jitter attenuation. The 2MHz bandwidth
provides the best tracking skew and will pass most spread profiles,
but the jitter attenuation will not be as good as the lower bandwidth
modes. Because some 2.5Gb serdes have x20 multipliers while
others have x25 multipliers, the 8741004 can be set for 1:1 mode or
5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the
F_SEL pins.
The 8741004 uses IDT’s 3
rd
Generation FemtoClock™
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making it
ideal for use in space constrained applications such as PCI Express
add-in cards.
Features
Two LVDS and two 0.7V differential output pairs
Bank A has two LVDS output pairs and
Bank B has two 0.7V differential output pairs
One differential clock input pair
CLK, CLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 98MHz - 160MHz
Input frequency range: 98MHz - 128MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 35ps (maximum)
Full 3.3V operating supply
Three bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
nQA1
QA1
V
DDO
QA0
nQA0
MR
BW_SEL
nc
V
DDA
F_SELA
V
DD
OEA
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQB1
QB1
V
DDO
QB0
nQB0
IREF
F_SELB
OEB
GND
GND
nCLK
CLK
PLL Bandwidth
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~600kHz (default)
1 = PLL Bandwidth: ~2MHz
8741004
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
8741004 Rev A 7/20/15
1
©2015 Integrated Device Technology, Inc.
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