response authentication and small message encryption
functionality with an implementation based on the FIPS
180-specified Secure Hash Algorithm (SHA-256). A 3Kb
user-programmable EEPROM array provides nonvola-
tile storage for application data and additional protected
memory holds a read-protected secret for SHA-256 oper-
ations and settings for user memory control. Each device
has its own guaranteed unique and unalterable 64-bit
ROM identification number (ROM ID) that is factory pro-
grammed into the chip. This unique ROM ID is used as a
fundamental input parameter for cryptographic operations
and also serves as an electronic serial number within the
application. A bidirectional security model enables two-
way authentication and encryption between a host system
and slave-embedded DS28C22. Slave-to-host authenti-
cation is used by a host system to securely validate that
an attached or embedded DS28C22 is authentic. Host-
to-slave authentication is used to protect DS28C22 user
memory from being modified by a nonauthentic host. The
SHA-256 message authentication code (MAC), which the
DS28C22 generates, is computed from data in the user
memory, an on-chip secret, a host random challenge, and
the 64-bit ROM ID. The device also facilitates encrypted
read and write between host and slave using a one time
pad computed by the SHA-256 engine. When not in use,
the DS28C22 can be put in sleep mode where power
consumption is minimal.
Benefits and Features
● Symmetric Key-Based Bidirectional Secure
Authentication and Encryption Model Based
on SHA-256
● Dedicated Hardware-Accelerated SHA Engine for
Generating SHA-256 MACs
● Strong Authentication with a 256-Bit, User-
Programmable Secret, and Input Challenge
● 3072 Bits of User EEPROM Partitioned Into 12
Pages of 256 Bits
● User-Programmable and Irreversible EEPROM
Protection Modes Including Authentication, Write
and Read Protect, Encryption, and OTP/EPROM
Emulation
● Supports 100kHz and 400kHz I
2
C Communication
Speeds
● Supports Power-Saving Sleep Mode at 0.5µA (typ)
● Operating Range: 3.3V ±10%, -40°C to +85°C
● 8-Pin TDFN Package
Ordering Information
appears at end of data sheet.
For related parts and recommended products to use with this part, refer
to
www.maximintegrated.com/DS28C22.related.
Typical Application Circuit
3.3V
R
P
(I
2
C PORT)
µC
SDA
SCL
V
CC
Applications
●
●
●
●
Authentication of Network-Attached Appliances
System Intellectual Property Protection
Secure Feature Setting for Configurable Systems
K
ey Generation and Secure Exchange for Crypto-
graphic Systems
DS28C22
SLPZ
DeepCover is a registered trademark of Maxim Integrated
Products, Inc.
R
P
= 1.1kΩ
MAXIMUM I
2
C BUS CAPACITANCE 320pF
219-0029; Rev 2; 7/13
ABRIDGED DATA SHEET
DS28C22
DeepCover Secure Memory with I
2
C SHA-256
and 3Kb User EEPROM
Absolute Maximum Ratings
Voltage Range on Any Pin Relative to GND
........-0.5V to +4.0V
Maximum Current into Any Pin...........................................20mA
Operating Temperature Range ..........................
-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................
-55°C to +125°C
Lead Temperature (soldering, 10s) .................................
+300°C
Soldering Temperature (reflow) ......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (θ
JA
) ..........60°C/W
Junction-to-Case Thermal Resistance (θ
JC
) ...............11°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(T
A
= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
Supply Voltage
Supply Current
SHA-256 Engine
Computation Current
Computation Time
EEPROM
Programming Current
Programming Time for 32-Bit
Segment
Write/Erase Cycling Endurance
Data Retention
SLPZ Pin
LOW Level Input Voltage
HIGH Level Input Voltage
Input Leakage Current
Wakeup Time from Sleep Mode
I
2
C SCL and SDA Pins (Note 12)
LOW Level Input Voltage
HIGH Level Input Voltage
V
IL
V
IH
I
I
t
SWUP
V
IL
V
IH
Pin at 3.63V
(Note 11)
-0.5
0.7 x
V
CC
-0.5
0.7 x
V
CC
0.3 x V
CC
V
CC
+
0.5V
0.1
250
0.3 x V
CC
V
CC(MAX)
+ 0.5V
V
V
µA
µs
V
V
I
PROG
t
PROG
N
CY
t
DR
(Notes 4, 5)
Refer to the full data sheet.
T
A
= +85°C (Notes 6, 7)
T
A
= +85°C (Notes 8, 9, 10)
1000
10
2
mA
ms
—
years
I
CSHA
t
CSHA
Refer to the full data sheet.
mA
ms
SYMBOL
V
CC
I
CC
(Note 3)
Sleep mode (SLPZ pin low), V
CC
= 3.63V
0.5
CONDITIONS
MIN
2.97
TYP
3.3
MAX
3.63
750
2.0
UNITS
V
µA
www.maximintegrated.com
Maxim Integrated │
2
ABRIDGED DATA SHEET
DS28C22
DeepCover Secure Memory with I
2
C SHA-256
and 3Kb User EEPROM
Electrical Characteristics (continued)
(T
A
= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
Hysteresis of Schmitt Trigger
Inputs
LOW Level Output Voltage at
3mA Sink Current
Output Fall Time from V
IH(MIN)
to
V
IL(MAX)
with Bus Capacitance
from 10pF to 400pF
Pulse Width of Spikes
Suppressed by the Input Filter
Input Current with Input Voltage
Between 0.1V
CC(MAX)
and
0.9V
CC(MAX)
Input Capacitance
SCL Clock Frequency
Hold Time (Repeated) START
Condition, After This Period, First
Clock Pulse Generated
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for Repeated START
Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between STOP
and START Condition
Capacitive Load for Each Bus
Line
Oscillator Warm-Up Time
SYMBOL
V
HYS
V
OL
t
OF
t
SP
I
I
C
I
f
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
BUF
C
b
t
OSCWUP
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Notes 4, 14, 15)
(Notes 4, 16)
(Note 4)
(Note 4)
(Notes 4, 17)
(Note 11)
250
0.6
1.3
400
250
(Note 4)
(Note 4)
(Notes 4, 13)
(Note 4)
0
0.6
1.3
0.6
0.6
0.9
-10
60
(Note 4)
CONDITIONS
MIN
0.05 x
V
CC
0.4
300
50
+10
10
400
TYP
MAX
UNITS
V
V
ns
ns
µA
pF
kHz
µs
µs
µs
µs
µs
ns
µs
µs
pF
µs
Note 2:
Limits are 100% production tested at T
A
= +25°C and T
A
= +85°C. Limits over the operating temperature range and rel-
evant supply voltage range are guaranteed by design and characterization.
Note 3:
Operating current continuously reading the Memory/MAC Read/Write Register at 400kHz.
Note 4:
Guaranteed by design and/or characterization only. Not production tested.
Note 5: Refer to the full data sheet.
Note 6:
Write-cycle endurance is tested in compliance with JESD47G.
Note 7:
Not 100% production tested; guaranteed by reliability monitor sampling.
Note 8:
Data retention is tested in compliance with JESD47G.
Note 9:
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 10: EEPROM Writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-
peratures is not recommended.
Note 11:
I
2
C communication should not take place for the max t
OSCWUP
or t
SWUP
time following a power-on reset or a wake-up
from sleep mode.
www.maximintegrated.com
Maxim Integrated │
3
ABRIDGED DATA SHEET
DS28C22
DeepCover Secure Memory with I
2
C SHA-256
and 3Kb User EEPROM
Electrical Characteristics (continued)
(T
A
= -40°C to +85°C, unless otherwise noted.) (Note 2)
Note 12:
All I
2
C timing values are referred to V
IH(MIN)
and V
IL(MAX)
levels.
Note 13: I/O pins of the DS28C22 do not obstruct the SDA and SCL lines if V
CC
is switched off.
Note 14: The DS28C22 provides a hold time of at least 300ns for the SDA signal (referred to the V
IH(MIN)
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 15: The maximum t
HD
:
DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal. If the
clock stretches the SCL, the data must be valid by the setup time before it releases the clock. (I
2
C-bus specification Rev.
03, 19 June 2007)
Note 16:
A fast-mode I
2
C-bus device can be used in a standard-mode I
2
C-bus system, but the requirement t
SU:DAT
≥ 250ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + t
SU:DAT
=
1000 + 250 = 1250ns (according to the standard-mode I
2
C-bus specification) before the SCL line is released. Also the
acknowledge timing must meet this setup time. (I
2
C-bus specification Rev. 03, 19 June 2007)
Note 17:
C
B
= total capacitance of one bus line in pF. The maximum bus capacitance allowable may vary from this value depending
on the actual operating voltage and frequency of the application. (I
2
C-bus specification Rev. 03, 19 June 2007)
Pin Configuration
TOP VIEW
GND N.C. V
CC
N.C.
8
7
6
5
8
7
6
5
Pin Description
PIN
TOP MARKING
1
2
NAME
SCL
SDA
FUNCTION
I
2
C Serial Clock Input. Must be connected
to V
CC
through a pullup resistor.
I
2
C Serial Data Input/Output. Must be
connected to V
CC
through a pullup
resistor.
Active-low control input to activate the
low-power sleep mode, and to issue a
device reset.
No Connection
Power-Supply Input
Ground Reference
Exposed Pad. Solder evenly to the
board’s ground plane for proper
operation. Refer to Application Note 3273:
Exposed Pads: A Brief Introduction
for
additional information.
DS28C22
28C22
ymrrF
3
4, 5, 7
6
8
SLPZ
N.C.
V
CC
GND
+
1
2
3
EP
+
1
2
3
EP
4
4
SCL SDA SLPZ N.C.
TDFN
—
EP
www.maximintegrated.com
Maxim Integrated │
4
ABRIDGED DATA SHEET
DS28C22
DeepCover Secure Memory with I
2
C SHA-256
and 3Kb User EEPROM
Package Information
Ordering Information
PIN-PACKAGE
8 TDFN-EP
*
DS28C22Q+T
-40°C to +85°C
(2.5k pcs)
+ Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*
EP = Exposed pad.
PART
TEMP RANGE
For the latest package outline information and land patterns
(footprints), go to
www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
8 TDFN-EP
PACKAGE
CODE
T823+1
OUTLINE
NO.
21-0174
LAND
PATTERN NO.
90-0091
Note to readers:
This document is an abridged version of the full data sheet. Additional device information is available
only in the full version of the data sheet. To request the full data sheet, go to
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