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PI6C4511WEX

Description
Phase Locked Loops - PLL Clock Multiplier
CategoryTopical application    Wireless rf/communication   
File Size100KB,5 Pages
ManufacturerDiodes Incorporated
Environmental Compliance
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PI6C4511WEX Overview

Phase Locked Loops - PLL Clock Multiplier

PI6C4511WEX Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerDiodes Incorporated
Product CategoryPhase Locked Loops - PLL
RoHSDetails
TypePLL Clock Multiplier
Number of Circuits1
Maximum Input Frequency50 MHz
Minimum Input Frequency4 MHz
Output Frequency Range200 MHz
Supply Voltage - Max5.5 V
Supply Voltage - Min3 V
Minimum Operating Temperature0 C
Maximum Operating Temperature+ 70 C
Mounting StyleSMD/SMT
Package / CaseSOIC-8
PackagingCut Tape
PackagingMouseReel
PackagingReel
Height1.5 mm
Length5 mm
Width3.99 mm
Operating Supply Voltage3.3 V, 5 V
Factory Pack Quantity3000
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2504A
Phase-Locked Loop Clock Driver
with 4 Clock Outputs
Product Features
High-Performance Phase-Locked-Loop Clock
Distribution for Networking
Registered DIMM Synchronous DRAM modules
for server/workstation/PC applications
Allows Clock Input to have Spread Spectrum
modulation for EMI reduction
Zero Input-to-Output delay
Low jitter: Cycle-to-Cycle jitter ±75ps max.
On-chip series damping resistor at clock output
drivers for low noise and EMI reduction
Operates at 3.3V V
CC
Wide range of Clock Frequencies 80 to 134 MHz
Package: Plastic 16-pin QSOP Package (Q)
Plastic 16-pin QSOP Package (QE) Pb-free
Product Description
The PI6C2504A features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver, distributing high-frequency clock signals for
SDRAM and server applications. By connecting the feedback
FB_OUT output to the feedback FB_IN input, the propagation
delay from the CLK_IN input to any clock output will be nearly zero.
Logic Block Diagram
G
4
PLL
FB_IN
AVCC
FB_OUT
Y[0:3]
Product Pin Configuration
AGND
VCC
Y0
Y1
GND
1
2
3
4
5
6
7
8
16
15
14
CLK_IN
AVCC
GND
GND
Y3
Y2
VCC
FB_IN
CLK_IN
16-Pin
Q
13
12
11
10
9
Functional Table
Inputs
G
L
H
Y[0:3]
L
CLK_IN
Outputs
FB_OUT
CLK_IN
CLK_IN
VCC
G
FB_OUT
1
PS8501A
09/19/05

PI6C4511WEX Related Products

PI6C4511WEX PI6C2404A-1WIEX PI6C103HE
Description Phase Locked Loops - PLL Clock Multiplier Phase Locked Loops - PLL 1:4 Zero Delay Clock Buffer Phase Locked Loops - PLL Mobile Clck Generatr
Product Attribute Attribute Value Attribute Value Attribute Value
Manufacturer Diodes Incorporated Diodes Incorporated Diodes Incorporated
Product Category Phase Locked Loops - PLL Phase Locked Loops - PLL Phase Locked Loops - PLL
RoHS Details Details Details
Type PLL Clock Multiplier Zero Delay PLL Clock Buffer PLL Clock Synthesizer
Number of Circuits 1 1 2
Output Frequency Range 200 MHz 10 MHz to 133 MHz 24 MHz to 100 MHz
Supply Voltage - Max 5.5 V 3.6 V 2.625 V, 3.465 V
Supply Voltage - Min 3 V 3 V 2.375 V, 3.135 V
Minimum Operating Temperature 0 C - 40 C 0 C
Maximum Operating Temperature + 70 C + 85 C + 70 C
Mounting Style SMD/SMT SMD/SMT SMD/SMT
Package / Case SOIC-8 SOIC-8 SSOP-28
Height 1.5 mm 1.5 mm 1.75 mm
Length 5 mm 5 mm 10.2 mm
Width 3.99 mm 3.99 mm 5.3 mm
Operating Supply Voltage 3.3 V, 5 V 3.3 V 2.5 V, 3.3 V
Factory Pack Quantity 3000 3000 47
Minimum Input Frequency 4 MHz - 100 MHz, 66.6 MHz, 14.318 MHz
Packaging Reel Reel Tube
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