EP1SGX25DF672C7 datasheet, PDF

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EP1SGX25DF672C7: DescriptionFPGA - Field Programmable Gate Array FPGA - Stratix I GX 2566 LABs 455 IOs; CategoryProgrammable logic devices Programmable logic; File Size1MB，262 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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FPGA - Field Programmable Gate Array FPGA - Stratix I GX 2566 LABs 455 IOs

EP1SGX25DF672C7 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
package instruction	27 X 27 MM, 1 MM PITCH, FBGA-672
Reach Compliance Code	compliant
ECCN code	3A001.A.7.A
JESD-30 code	S-PBGA-B672
JESD-609 code	e0
length	27 mm
Humidity sensitivity level	3
Configurable number of logic blocks	2852
Number of entries	462
Number of logical units	25660
Output times	462
Number of terminals	672
Maximum operating temperature	85 °C
Minimum operating temperature
organize	2852 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA672,26X26,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	220
power supply	1.5,1.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	27 mm

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Stratix GX FPGA Family

December 2004, ver. 2.2

Data Sheet

Introduction

The Stratix

GX family of devices is Altera’s second FPGA family to

combine high-speed serial transceivers with a scalable, high-performance

logic array. Stratix GX devices include 4 to 20 high-speed transceiver

channels, each incorporating clock data recovery (CDR) technology and

embedded SERDES capability at data rates of up to 3.1875 gigabits per

second (Gbps). These transceivers are grouped by four-channel

transceiver blocks, and are designed for low power consumption and

small die size. The Stratix GX FPGA technology is built upon the Stratix

architecture, and offers a 1.5-V logic array with unmatched performance,

flexibility, and time-to-market capabilities. This scalable,

high-performance architecture makes Stratix GX devices ideal for

high-speed backplane interface, chip-to-chip, and communications

protocol-bridging applications.

■

Features

Transceiver block features are as follows:

●

High-speed serial transceiver channels with CDR provides

500-megabits per second (Mbps) to 3.1875-Gbps full-duplex

operation

●

Devices are available with 4, 8, 16, or 20 high-speed serial

transceiver channels providing up to 127.5 Gbps of full-duplex

serial bandwidth

●

Support for transceiver-based protocols, including 10 Gigabit

Ethernet attachment unit interface (XAUI), Gigabit Ethernet

(GigE), and SONET/SDH

●

Compatible with PCI Express, SMPTE 292M, Fibre Channel, and

Serial RapidIO I/O standards

●

Programmable differential output voltage (V

), pre-emphasis,

and equalization settings for improved signal integrity

●

Individual transmitter and receiver channel power-down

capability implemented automatically by the Quartus

software for reduced power consumption during non-operation

●

Programmable transceiver-to-FPGA interface with support for

8-, 10-, 16-, and 20-bit wide data paths

●

1.5-V pseudo current mode logic (PCML) for 500 Mbps to

3.1875 Gbps

●

Support for LVDS, LVPECL, and 3.3-V PCML on reference

clocks and receiver input pins (AC-coupled)

●

Built-in self test (BIST)

●

Hot insertion/removal protection circuitry

Altera Corporation

DS-STXGX-2.2

Preliminary

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