74HC191PW datasheet, PDF - EEWORLD Datasheet

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74HC191PW: DescriptionCounter ICs SYNC BIN U/D COUNTER; Categorylogic logic; File Size399KB，23 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74HC191PW Overview

Counter ICs SYNC BIN U/D COUNTER

74HC191PW Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP16,.25
Contacts	16
Reach Compliance Code	compliant
Other features	TCO OUTPUT
Counting direction	BIDIRECTIONAL
series	HC/UH
JESD-30 code	R-PDSO-G16
JESD-609 code	e4
length	5 mm
Load capacitance (CL)	50 pF
Load/preset input	YES
Logic integrated circuit type	BINARY COUNTER
Maximum Frequency@Nom-Sup	16000000 Hz
MaximumI(ol)	0.004 A
Operating mode	SYNCHRONOUS
Humidity sensitivity level	1
Number of digits	4
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	2/6 V
propagation delay (tpd)	66 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	4.4 mm
minfmax	13 MHz
Base Number Matches	1

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Important notice

Dear Customer,

On 7 February 2017 the former NXP Standard Product business became a new company with the

tradename

Nexperia.

Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS

semiconductors with its focus on the automotive, industrial, computing, consumer and wearable

application markets

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use

the references to Nexperia, as shown below.

Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,

use

http://www.nexperia.com

Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use

salesaddresses@nexperia.com

(email)

Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on

the version, as shown below:

reserved

Should be replaced with:

If you have any questions related to the data sheet, please contact our nearest sales office via e-mail

or telephone (details via

salesaddresses@nexperia.com).

Thank you for your cooperation and

understanding,

Kind regards,

Team Nexperia

74HC191

Presettable synchronous 4-bit binary up/down counter

Rev. 3 — 3 January 2017

Product data sheet

1. General description

The 74HC191 is an asynchronously presettable 4-bit binary up/down counter. It contains

four master/slave flip-flops with internal gating and steering logic to provide asynchronous

preset and synchronous count-up and count-down operation. Asynchronous parallel load

capability permits the counter to be preset to any desired value. Information present on

the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs

when the parallel load (PL) input is LOW. This operation overrides the counting function.

Counting is inhibited by a HIGH level on the count enable (CE) input. When CE is LOW

internal state changes are initiated synchronously by the LOW-to-HIGH transition of the

clock input. The up/down (U/D) input signal determines the direction of counting as

indicated in the function table. The CE input may go LOW when the clock is in either state,

however, the LOW-to-HIGH CE transition must occur only when the clock is HIGH. Also,

the U/D input should be changed only when either CE or CP is HIGH. Overflow/underflow

indications are provided by two types of outputs, the terminal count (TC) and ripple clock

(RC). The TC output is normally LOW and goes HIGH when a circuit reaches zero in the

count-down mode or reaches '15' in the count-up-mode. The TC output will remain HIGH

until a state change occurs, either by counting or presetting, or until U/D is changed. Do

not use the TC output as a clock signal because it is subject to decoding spikes. The TC

signal is used internally to enable the RC output. When TC is HIGH and CE is LOW, the

RC output follows the clock pulse (CP). This feature simplifies the design of multistage

counters as shown in

Figure 5

and

Figure 6.

Figure 5,

each RC output is used as the

clock input to the next higher stage. It is only necessary to inhibit the first stage to prevent

counting in all stages, since a HIGH on CE inhibits the RC output pulse. The timing skew

between state changes in the first and last stages is represented by the cumulative delay

of the clock as it ripples through the preceding stages. This can be a disadvantage of this

configuration in some applications.

Figure 6

shows a method of causing state changes to

occur simultaneously in all stages. The RC outputs propagate the carry/borrow signals in

ripple fashion and all clock inputs are driven in parallel. In this configuration the duration of

the clock LOW state must be long enough to allow the negative-going edge of the

carry/borrow signal to ripple through to the last stage before the clock goes HIGH. Since

the RC output of any package goes HIGH shortly after its CP input goes HIGH there is no

such restriction on the HIGH-state duration of the clock. In

Figure 7,

the configuration

shown avoids ripple delays and their associated restrictions. Combining the TC signals

from all the preceding stages forms the CE input for a given stage. An enable must be

included in each carry gate in order to inhibit counting. The TC output of a given stage it

not affected by its own CE signal therefore the simple inhibit scheme of

Figure 5

and

Figure 6

does not apply. Inputs include clamp diodes. This enables the use of current

limiting resistors to interface inputs to voltages in excess of V

74HC191PW Related Products

	74HC191PW	74HC191DB,112
Description	Counter ICs SYNC BIN U/D COUNTER	Counter ICs SYNC BIN U/D COUNTER
Is it Rohs certified?	conform to	conform to
Maker	NXP	NXP
Parts packaging code	TSSOP	SSOP1
package instruction	TSSOP, TSSOP16,.25	SSOP, SSOP16,.3
Contacts	16	16
Reach Compliance Code	compliant	compliant
Other features	TCO OUTPUT	TCO OUTPUT
Counting direction	BIDIRECTIONAL	BIDIRECTIONAL
series	HC/UH	HC/UH
JESD-30 code	R-PDSO-G16	R-PDSO-G16
JESD-609 code	e4	e4
length	5 mm	6.2 mm
Load capacitance (CL)	50 pF	50 pF
Load/preset input	YES	YES
Logic integrated circuit type	BINARY COUNTER	BINARY COUNTER
Maximum Frequency@Nom-Sup	16000000 Hz	16000000 Hz
MaximumI(ol)	0.004 A	0.004 A
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Humidity sensitivity level	1	1
Number of digits	4	4
Number of functions	1	1
Number of terminals	16	16
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	SSOP
Encapsulate equivalent code	TSSOP16,.25	SSOP16,.3
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	260
power supply	2/6 V	2/6 V
propagation delay (tpd)	66 ns	66 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	2 mm
Maximum supply voltage (Vsup)	6 V	6 V
Minimum supply voltage (Vsup)	2 V	2 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	30	30
Trigger type	POSITIVE EDGE	POSITIVE EDGE
width	4.4 mm	5.3 mm
minfmax	13 MHz	13 MHz
Base Number Matches	1	1

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