PI7C8152A & PI7C8152B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
LIFE SUPPORT POLICY
Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life
support devices or systems unless a specific written agreement pertaining to such intended use is executed
between the manufacturer and an officer of PSC.
1) Life support devices or system are devices or systems which:
a) Are intended for surgical implant into the body or
b) Support or sustain life and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2) A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products
or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom Semiconductor does not assume any responsibility for use of any
circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The
Company makes no representations that circuitry described herein is free from patent infringement or
other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation.
All other trademarks are of their respective companies.
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October 16, 2003 – Revision 1.11
14-0055
PI7C8152A & PI7C8152B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
TABLE OF CONTENTS
1
2
INTRODUCTION .............................................................................................................................. 11
SIGNAL DEFINITIONS ................................................................................................................... 12
2.1
S
IGNAL
T
YPES
............................................................................................................................... 12
2.2
S
IGNALS
........................................................................................................................................ 12
2.2.1
PRIMARY BUS INTERFACE SIGNALS
.......................................................................... 12
2.2.3
CLOCK SIGNALS
............................................................................................................... 15
2.2.4
MISCELLANEOUS SIGNALS...........................................................................................
15
2.2.5
POWER AND GROUND.....................................................................................................
16
2.3
PIN LIST – 160-PIN MQFP.......................................................................................................... 16
3
PCI BUS OPERATION ..................................................................................................................... 17
3.1
TYPES OF TRANSACTIONS ..................................................................................................... 17
3.2
SINGLE ADDRESS PHASE........................................................................................................ 18
3.3
DUAL ADDRESS PHASE........................................................................................................... 18
3.4
DEVICE SELECT (DEVSEL_L) GENERATION....................................................................... 19
3.5
DATA PHASE.............................................................................................................................. 19
3.6
WRITE TRANSACTIONS .......................................................................................................... 19
3.6.1
MEMORY WRITE TRANSACTIONS................................................................................
20
3.6.2
MEMORY WRITE AND INVALIDATE
............................................................................ 21
3.6.3
DELAYED WRITE TRANSACTIONS...............................................................................
21
3.6.4
WRITE TRANSACTION ADDRESS BOUNDARIES.......................................................
22
3.6.5
BUFFERING MULTIPLE WRITE TRANSACTIONS.....................................................
22
3.6.6
FAST BACK-TO-BACK WRITE TRANSACTIONS
......................................................... 23
3.7
READ TRANSACTIONS ............................................................................................................ 23
3.7.1
PREFETCHABLE READ TRANSACTIONS....................................................................
23
3.7.2
NON-PREFETCHABLE READ TRANSACTIONS..........................................................
23
3.7.3
READ PREFETCH ADDRESS BOUNDARIES
............................................................... 24
3.7.4
DELAYED READ REQUESTS
.......................................................................................... 24
3.7.5
DELAYED READ COMPLETION ON TARGET BUS
.................................................... 25
3.7.6
DELAYED READ COMPLETION ON INITIATOR BUS................................................
25
3.7.7
FAST BACK-TO-BACK READ TRANSACTION
............................................................. 26
3.8
CONFIGURATION TRANSACTIONS ...................................................................................... 26
3.8.1
TYPE 0 ACCESS TO PI7C8152x
....................................................................................... 27
3.8.2
TYPE 1 TO TYPE 0 CONVERSION
.................................................................................. 27
3.8.3
TYPE 1 TO TYPE 1 FORWARDING.................................................................................
29
3.8.4
SPECIAL CYCLES
............................................................................................................. 30
3.9
TRANSACTION TERMINATION.............................................................................................. 30
3.9.1
MASTER TERMINATION INITIATED BY PI7C8152x..................................................
31
3.9.2
MASTER ABORT RECEIVED BY PI7C8152x.................................................................
32
3.9.3
TARGET TERMINATION RECEIVED BY PI7C8152x
.................................................. 32
3.9.4
TARGET TERMINATION INITIATED BY PI7C8152x
.................................................. 35
4
ADDRESS DECODING..................................................................................................................... 36
4.1
ADDRESS RANGES ................................................................................................................... 37
4.2
I/O ADDRESS DECODING ........................................................................................................ 37
4.2.1
I/O BASE AND LIMIT ADDRESS REGISTER................................................................
38
4.2.2
ISA MODE...........................................................................................................................
38
4.3
MEMORY ADDRESS DECODING............................................................................................ 39
4.3.1
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS
......................... 39
4.3.2
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS
................. 40
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October 16, 2003 – Revision 1.11
14-0055
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