Philips Semiconductors
Product data
13-bit GTL–/GTL/GTL+ to LVTTL translator
GTL2006
FEATURES
•
Operates as a GTL–/GTL/GTL+ to LVTTL sampling receiver or
•
3.0 V to 3.6 V operation
•
LVTTL I/O not 5 V tolerant
•
Series termination on the LVTTL outputs of 30
Ω
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 250 V CDM per JESD22-C101
LVTTL to GTL–/GTL/GTL+ driver
PIN CONFIGURATION
V
REF
1
1AO 2
2AO 3
5A 4
6A 5
8AI 6
11BI 7
11A 8
9BI 9
3AO 10
4AO 11
10AI1 12
10AI2 13
GND 14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
1BI
2BI
7BO1
7BO2
8BO
11BO
5BI
6BI
3BI
4BI
10BOI
10BO2
9AO
•
Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 500 mA
•
Package offered: TSSOP28
DESCRIPTION
The GTL2006 is a 13-bit translator to interface between the 3.3 V
LVTTL chip set I/O and the Xeon™ processor GTL–/GTL/GTL+ I/O.
The GTL2006 is designed for platform health management in dual
processor applications.
SW01091
Figure 1. Pin configuration
PIN DESCRIPTION
PIN NUMBER
1
2–6, 8,
10–13, 15
7, 9, 16,
17–27
14
28
SYMBOL
V
REF
nAn
nBn
GND
V
CC
NAME AND FUNCTION
GTL reference voltage
Data inputs/outputs
(LVTTL)
Data inputs/outputs
(GTL–/GTL/GTL+)
Ground (0 V)
Positive supply voltage
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
I/O
PARAMETER
Propagation delay
An to Bn or Bn to An
I/O pin capacitance
CONDITIONS
T
amb
= 25
°C
C
L
= 50 pF; V
CC
= 3.3 V
Outputs disabled; V
I/O
= 0 V or 3.0 V
TYPICAL
UNIT
B to A
5.5
7.8
A to B
5.5
4.5
ns
pF
ORDERING INFORMATION
PACKAGES
28-Pin Plastic TSSOP
TEMPERATURE RANGE
–40
°C
to +85
°C
ORDER CODE
GTL2006PW
TOPSIDE MARK
GTL2006
DWG NUMBER
SOT361-1
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
2004 Jun 21
2
Philips Semiconductors
Product data
13-bit GTL–/GTL/GTL+ to LVTTL translator
GTL2006
FUNCTION TABLES
INPUT
1BI/2BI/3BI/4BI/9BI
L
H
INPUT
10AI1/10AI2
L
L
H
H
OUTPUT
1AO/2AO/3AO/4AO/9AO
L
H
INPUT
9BI
L
H
L
H
INPUT
8AI
L
H
OUTPUT
10BO1/10BO2
L
L
L
H
OUTPUT
8BO
L
H
INPUT
5BI/6BI
L
H
H
INPUT/OUTPUT
5A/6A (OPEN DRAIN)
L
L
2
H
OUTPUT
7BO1/7BO2
H
1
L
H
INPUT
11BI
L
L
H
INPUT/OUTPUT
11A (OPEN DRAIN)
H
L
2
L
OUTPUT
11BO
L
H
H
H = HIGH voltage level
L = LOW voltage level
NOTES:
1. The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH
on 5A/6A lags up to 100 ns from causing a low glitch on the 7BO1/7BO2 outputs.
2. Open Drain Input/Output terminal is driven to logic LOW state by other driver.
2004 Jun 21
3
Philips Semiconductors
Product data
13-bit GTL–/GTL/GTL+ to LVTTL translator
GTL2006
LOGIC SYMBOL
GTL2006
GTL V
REF
1AO
LVTTL
OUTPUTS
2AO
3
1
2
27
1BI
GTL
INPUTS
2BI
26
5A (OPEN DRAIN)
LVTTL I/O
6A (OPEN DRAIN)
4
25
7BO1
5
24
7BO2
GTL
OUTPUTS
LVTTL INPUT 8AI
GTL INPUT 11BI
6
7
23
22
DELAY
1
21
8BO
11BO
LVTTL I/O 11A (OPEN DRAIN)
8
9
5BI
GTL INPUT 9BI
DELAY
1
20
6BI
GTL
INPUTS
3AO
LVTTL
OUTPUTS
4AO
10
19
3BI
11
18
4BI
17
10AI1
LVTTL
INPUTS
10AI2
12
16
13
10BO1
GTL
OUTPUTS
10BO2
15
9AO LVTTL OUTPUT
SW01092
NOTE:
1. The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH
on 5A/6A lags up to 100 ns from causing a low glitch on the 7BO1/7BO2 outputs.
Figure 2. Logic symbol
2004 Jun 21
4
Embedded System
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