5962F1120201QXA datasheet, PDF

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5962F1120201QXA: DescriptionQDR SRAM, 2MX36, 0.85ns, CMOS, CBGA165, 21 X 25 MM, 2.83 MM HEIGHT, CERAMIC, MO-158BE-1, CGA-165; Categorystorage storage; File Size459KB，35 Pages; ManufacturerCypress Semiconductor

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5962F1120201QXA Overview

QDR SRAM, 2MX36, 0.85ns, CMOS, CBGA165, 21 X 25 MM, 2.83 MM HEIGHT, CERAMIC, MO-158BE-1, CGA-165

5962F1120201QXA Parametric

Parameter Name	Attribute value
Objectid	1288119072
package instruction	CGA, CGA165,11X15,50
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	0.85 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	250 MHz
I/O type	SEPARATE
JESD-30 code	R-CBGA-X165
length	25 mm
memory density	75497472 bit
Memory IC Type	QDR SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	2MX36
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	CGA
Encapsulate equivalent code	CGA165,11X15,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
power supply	1.8 V
Certification status	Not Qualified
Filter level	MIL-STD-883
Maximum seat height	5.38 mm
Maximum standby current	0.66 A
Maximum slew rate	1.7 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	UNSPECIFIED
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	21 mm

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72-Mbit QDR II+ SRAM

Two-Word Burst Architecture

with RadStop™ Technology

72-Mbit QDR

II+ SRAM Two-Word Burst Architecture with RadStop™ Technology

CYRS1542AV18

CYRS1544AV18

Radiation Performance

Radiation Data

■

JTAG 1149.1 compatible test access port

DLL for accurate data placement

Total Dose

=300

Krad

Soft error rate (both

Heavy Ion

and proton)

Heavy ions



1 × 10

-10

upsets/bit-day with an external SECDED

EDAC Controller

Neutrons

= 2.0 × 10

N/cm

Dose rate = 2.0 × 10

rad(Si)/sec

Dose rate survivability (rad(Si)/sec) = 1.5 × 10^11 rad(Si)/sec

Latch up immunity = 120 MeV.cm

/mg (125 °C)

Configurations

CYRS1542AV18 – 4M × 18

CYRS1544AV18 – 2M × 36

■

Functional Description

The CYRS1542AV18 and CYRS1544AV18 are synchronous

pipelined SRAMs, equipped with 1.8-V QDR II+ architecture with

RadStop™ technology. Cypress’s state-of-the-art

RadStop

Technology

is radiation hardened through proprietary design and

process hardening techniques.

The QDR II+ architecture consists of two separate ports to

access the memory: the read port and the write port. The read

port has dedicated data output bus to support read operations

and the write port has dedicated data input bus to support write

operations. QDR II+ architecture completely eliminates the need

to “turnaround” the data bus that exists with common I/O devices.

Each port is accessed through a common address bus.

Addresses for read are latched on the rising edges of the input

(K) clock whereas addresses for write are latched on the falling

edges of the input (K) clock. Accesses to the QDR II+ read and

write ports are completely independent of each another. To

maximize data throughput, both read and write ports are

equipped with DDR interfaces. Each address location is

associated with two 18-bit words for CYRS1542AV18, or two

36-bit words for CYRS1544AV18 that burst sequentially into or

out of the device. Since data can be transferred on every rising

edge of both input clocks (K and K#), memory bandwidth is

maximized while simplifying system design by eliminating bus

“turnarounds”.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks as well. Reads and

writes are conducted with on-chip synchronous self-timed

circuitry.

For a complete list of related resources,

click here.

Prototyping Options

■

Non qualified CYPT1542AV18 and CTPT1544AV18 devices

with same functional and timing characteristics in a

165-ball

Ceramic Column Grid Array

(CCGA) package and Land Grid

Array (LGA) package without solder columns attached.

Features

■

Separate independent read and write data ports

❐

Supports concurrent transactions

250-MHz clock for high bandwidth

Two-word burst on all accesses

Double data rate (DDR) interfaces on both read and write ports

at 250 MHz (data transferred at 500 MHz)

Two input clocks (K and K) for precise DDR timing

❐

SRAM uses rising edges only

Echo clocks (CQ and CQ) simplify data capture in high speed

systems

Single multiplexed address input bus latches address inputs

for both read and write ports

Separate port selects for depth expansion

Synchronous internally self-timed writes

QDR

II operates with 2.0 cycle read latency when delay lock

loop (DLL) is enabled

Available in × 18 and × 36 configurations

Full data coherency, providing most current data

Core V

= 1.8 V (±0.1 V); I/O V

DDQ

= 1.4 V to V

Available in 165-ball CCGA (21 × 25 × 2.83 mm)

HSTL inputs and variable drive HSTL output buffers

■

Selection Guide

Description

Maximum operating frequency

Maximum operating current

(concurrent R/W)

× 18

× 36

250 MHz Unit

250

1700

MHz

Cypress Semiconductor Corporation

Document Number: 001-60006 Rev. *N

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised November 3, 2017

5962F1120201QXA Related Products

	5962F1120201QXA	CYRS1542AV18-250GCMB	5962F1120101QXA	CYPT1544AV18-250GCMB
Description	QDR SRAM, 2MX36, 0.85ns, CMOS, CBGA165, 21 X 25 MM, 2.83 MM HEIGHT, CERAMIC, MO-158BE-1, CGA-165	SRAM 72Mb 1.8V 250Mhz 4M x 18 QDR II SRAM	SRAM Sync SRAMs	SRAM 72Mb 1.8V 250Mhz 4M x 18 QDR II SRAM

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