DATASHEET
ZL9101M
Digital DC/DC PMBus 12A Module
The
ZL9101M
is a 12A, variable output, step-down
PMBus-compliant digital power supply. Included in the module
is a high-performance digital PWM controller, power MOSFETs,
an inductor, and all the passive components required for a
highly integrated DC/DC power solution. This power module
has built-in auto-compensation algorithms, which eliminate
the need for manual compensation design work. The ZL9101M
operates over a wide input voltage range and supports an
output voltage range of 0.6V to 3.6V, which can be set by
external resistors or through PMBus. This high-efficiency power
module is capable of delivering 12A. Only bulk input and
output capacitors are needed to finish the design. The output
voltage can be precisely regulated to as low as 0.6V with ±1%
output voltage regulation over line, load, and temperature
variations.
The ZL9101M features auto compensation, internal soft-start,
auto-recovery overcurrent protection, an enable option, and
prebiased output start-up capabilities.
The ZL9101M is packaged in a thermally enhanced, compact
(15mmx15mm) and low profile (3.5mm) overmolded QFN
package module suitable for automated assembly by standard
surface mount equipment. The ZL9101M is RoHS compliant.
Figure 1
represents a typical implementation of the ZL9101M.
For PMBus operation, it is recommended to tie the Enable pin
(EN) to SGND.
FN7669
Rev.8.00
Jun 20, 2017
Features
• Complete digital switch mode power supply
• Fast transient response
• Auto compensating PID filter
• External synchronization
• Output voltage tracking
• Current sharing
• Programmable soft-start delay and ramp
• Overcurrent/undercurrent protection
• PMBus compliant
Applications
• Server, telecom, and datacom
• Industrial and medical equipment
• General purpose point-of-load
Related Literature
• For a full list of related documents, visit our website
-
ZL9101M
product page
V
DR V
4.5V TO 6.5V
10µF
16V
4.7µF
16V
4.7µF
16V
10µF
16V
V
IN
4.5V TO 13.2V
C
IN
VDRV
POWE R GOO D OUTPUT
ENABLE
EXT SYNC
DDC BUS
PG
EN
VIN
(EPAD)
VOUT
(EPAD)
ZL9101M
VDD
VR
V25
V
OUT
SYNC
DDC
SCL
SW
(EPAD)
PGND
(EPAD)
FB+
FB-
C
OUT
RTN
SA
R
SA
R
SET
FIGURE 1. A COMPLETE DIGITAL SWITCH MODE POWER SUPPLY, ONLY BULK INPUT AND OUTPUT CAPACITORS ARE REQUIRED TO FINISH
THE DESIGN
FN7669 Rev.8.00
Jun 20, 2017
SGND
I C/SMBus
2
SDA
VTRK
VSE T
Page 1 of 63
ZL9101M
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical Application - Single Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Derating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
2
C/SMBus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adaptive Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
2
C/SMBus Module Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Adding/Dropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitoring Through I
2
C/SMBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nonvolatile Memory and Device Security Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
11
11
11
11
12
12
12
12
12
13
13
13
14
14
14
15
15
15
16
16
17
17
18
18
18
18
19
19
PMBus Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PMBus Use Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PMBus Commands Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Firmware Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
FN7669 Rev.8.00
Jun 20, 2017
Page 2 of 63
ZL9101M
Pin Configuration
ZL9101M
(21 LD QFN)
TOP VIEW
SGND
SYNC
DDC
SCL
PG
VR
EN
SA
9
PGND
V25
VDD
10
11
12
8
7
6
5
4
3
2
1
21
20
19
SDA
VSET
VTRK
FB+
VDRV
13
14
SW
VIN
15
PGND
16
18
FB-
VOUT
17
Pin Descriptions
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14 (epad)
15 (epad)
16 (epad)
17 (epad)
18
19
20
21
LABEL
SDA
SCL
SA
SYNC
PG
EN
DDC
VR
SGND
PGND
V25
VDD
VDRV
SW
VIN
PGND
VOUT
FB-
FB+
VTRK
VSET
TYPE
I/O
I/O
I
I/O
O
I
I/O
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
I
I
I
I
DESCRIPTION
Serial data. A pull-up resistor is required for this application.
Serial clock. A pull-up resistor is required for this application.
Serial address select pin. Used to assign a unique SMBus address to each module.
Clock synchronization. Used for synchronization to external frequency reference.
Power-good output.
Enable input (factory setting active high). Pull-up to enable PWM switching and pull-down to disable PWM switching.
Digital-DC bus (open drain). Interoperability between Intersil digital modules. A pull-up resistor is required for this
application.
Internal 5V reference used to power internal drivers. Connect a 4.7μF bypass capacitor to this pin.
Signal ground. Connect to low impedance ground plane.
Power ground. Connect to low impedance ground plane.
Internal 2.5V reference used to power internal circuitry. Connect a 4.7μF bypass capacitor to this pin.
Input supply voltage for controller. Connect a 4.7μF bypass capacitor to this pin.
Power supply for internal FET drivers. Connect a 10μF bypass capacitor to this pin.
Drive train switch node.
Power supply input FET voltage.
Power ground. Connect to low impedance ground plane.
Power supply output voltage. Output voltage from PWM.
Output voltage feedback. Connect to load return of ground regulation point.
Output voltage feedback. Connect to output regulation point.
Tracking sense input. Used to track an external voltage source.
Output voltage selection pin. Used to set V
OUT
set point and V
OUT
maximum.
FN7669 Rev.8.00
Jun 20, 2017
Page 3 of 63
ZL9101M
Internal Block Diagram
VDRV
VIN
GH
PWMH
BST
PWML
SW
0.22µH
VOUT
VDD
FB
VTRK
VSET
PG
SS
MGN
EN
LDO
LDO
OV/UV POWER MANAGEMENT
OC/UC
CURRENT SHARE
INTERLEAVE
AUTOCOMP
VDRV
SYNC
PLL
D-PWM
NVM
GATE DRIVE LOGIC
SYNC
OUT
V25
VR
SW
GL
GND
SUPERVISOR
NLR
DIGITAL
COMPENSATOR
POWER STAGE
GATE DRIVER
PROTECTION
CSA
22
SCL
SDA
DDC
SA
ADC
TEMP
SENSOR
DIGITAL CONTROLLER
PGND
SGND
COMMUNICATION
ADC
VSA
VDD
VDRV
22
FB-
FB+
SGND
DGND
FIGURE 2. ZL9101M INTERNAL BLOCK DIAGRAM
FN7669 Rev.8.00
Jun 20, 2017
Page 4 of 63
ZL9101M
Typical Application - Single Module
V
IN
4.5V TO 13.2V
330µF BULK
C
1
2x22µF
CERAMIC
C
2
VR
+
VIN
C
5
V
DD
4.5V TO 13.2V
V
DRV
4.5V TO 6.5V
V
LOGIC
3.0V TO 6.0V
10µF
CERAMIC
VDD
C
3
10µF
CERAMIC
10k
:
10k
:
4.7µF
CERAMIC
(
Note
VDRV
3
V25
C
6
4.7µF
CERAMIC
C
4
4.75k
:
ZL9101M
R
1
R
2
R
3
(
Notes
4x100µF
CERAMIC
2x330µF
POSCAP
VOUT
1
,
SCL
SDA
DDC
C
7
C
8
+
V
OUT
1.2V 12A
SCL
SDA
DDC
EN
VTRK
SYNC
FB-
R
4
= 200:
FB+
EN
VTRK
PGND
SA
SYNC
R
SA
= 51.1k
:
SMBUS ADD = 0x2A
R
SET
= 31.6k
:
V
OUT
= 1.2V
NOTES:
1. R
1
and R
2
are not required if the PMBus host already has I
2
C pull-up resistors.
2. Only one R
3
per DDC bus is required when DDC bus is shared with other modules.
3. The VR, V25, VDRV, and VDD capacitors should be placed no farther than 0.5cm from the pin.
4. R
4
is optional but recommended to sink possible ~100µA backflow current from the FB+ pin. Backflow current is present only when the
module is in a disabled state with power still available at the V
DD
pin.
FIGURE 3. SINGLE MODULE
FN7669 Rev.8.00
Jun 20, 2017
SGND
VSET
(
Note
4
)
Page 5 of 63
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