Features
•
Two Different IF Receiving Bandwidth Versions Are Available
•
•
•
•
•
•
•
•
•
•
•
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•
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(B
IF
= 300 kHz or 600 kHz)
Frequency Receiving Range of
f
0
= 868 MHz to 870 MHz or f
0
= 902 MHz to 928 MHz
30 dB Image Rejection
Receiving Bandwidth B
IF
= 600 kHz for Low Cost 90-ppm Crystals and B
IF
= 300 kHz for
55 ppm Crystals
Fully Integrated LC-VCO and PLL Loop Filter
Very High Sensitivity with Power Matched LNA
High System IIP3 (–16 dBm), System 1-dB Compression Point (–25 dBm)
High Large-signal Capability at GSM Band
(Blocking –30 dBm at +20 MHz, IIP3 = –12 dBm at +20 MHz)
5V to 20V Automotive Compatible Data Interface
Data Clock Available for Manchester- and Bi-phase-coded Signals
Programmable Digital Noise Suppression
Low Power Consumption Due to Configurable Polling
Temperature Range –40°C to +105°C
ESD Protection 2 kV HBM, All Pins
Communication to Microcontroller Possible Via a Single Bi-directional Data Line
Low-cost Solution Due to High Integration Level with Minimum External Circuitry
Requirements
UHF ASK/FSK
Receiver
ATA5760
ATA5761
1. Description
The ATA5760/ATA5761 is a multi-chip PLL receiver device supplied in an SO20 pack-
age. It has been especially developed for the demands of RF low-cost data
transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or
Bi-phase code. The receiver is well suited to operate with the Atmel’s PLL RF trans-
mitter T5750. Its main applications are in the areas of telemetering, security
technology and keyless-entry systems. It can be used in the frequency receiving
range of f
0
= 868 MHz to 870 MHz or f
0
= 902 MHz to 928 MHz for ASK or FSK data
transmission. All the statements made below refer to 868.3 MHz and 915.0 MHz
applications.
Figure 1-1.
System Block Diagram
UHF ASK/FSK
Remote control receiver
UHF ASK/FSK
Remote control transmitter
T5750
ATA5760/
ATA5761
Demod.
PLL
IF Amp
Control
1...5
µC
XTO
Antenna
VCO
Antenna
PLL
XTO
Power
amp.
LNA
VCO
4896D–RKE–08/08
Figure 1-2.
Block Diagram
CDEM
FSK/ASK-
demodulator
and
data filter
Rssi
Limiter out
RSSI IF
Dem_out
Data -
interface
DATA
SENS
AVCC
AGND
DGND
DVCC
POLLING/_ON
Sensitivity-
reduction
Polling circuit
and
control logic
Amp.
DATA_CLK
4. Order
f0 = 950 kHz/
1 MHz
FE
CLK
IC_ACTIVE
LPF
fg = 2.2 MHz
Standby
logic
IF
Amp.
Loop-
filter
Poly-LPF
fg = 7 MHz
LC-VCO
XTO
XTAL
LNAREF
f
f
:2
:256
LNA_IN
LNAGND
LNA
2
ATA5760/ATA5761
4896D–RKE–08/08
ATA5760/ATA5761
2. Pin Configuration
Figure 2-1.
Pinning SO20
SENS
1
20
DATA
IC_ACTIVE
2
19
CDEM
3
18
DGND
AVCC
4
17
DATA_CLK
TEST 1
5
16
TEST 4
AGND
6
ATA5760/
ATA5761
15
DVCC
NC
7
14
XTAL
LNAREF
8
13
NC
LNA_IN
9
12
TEST 3
LNAGND 10
11
TEST 2
Table 2-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Description
Symbol
SENS
IC_ACTIVE
CDEM
AVCC
TEST 1
AGND
NC
LNAREF
LNA_IN
LNAGND
TEST 2
TEST 3
NC
XTAL
DVCC
TEST 4
DATA_CLK
DGND
POLLING/_ON
DATA
Function
Sensitivity-control resistor
IC condition indicator: Low = sleep mode, High = active mode
Lower cut-off frequency data filter
Analog power supply
Test pin, during operation at GND
Analog ground
Not connected, connect to GND
High-frequency reference node LNA and mixer
RF input
DC ground LNA and mixer
Do not connect during operating
Test pin, during operation at GND
Not connected, connect to GND
Crystal oscillator XTAL connection
Digital power supply
Test pin, during operation at DVCC
Bit clock of data stream
Digital ground
Selects polling or receiving mode; Low: receiving mode, High: polling mode
Data output/configuration input
3
4896D–RKE–08/08
3. RF Front End
The RF front end of the receiver is a low-IF heterodyne configuration that converts the input sig-
nal into an about 1 MHz IF signal with an image rejection of typical 30 dB. According to
Figure
2-1 on page 3
the front end consists of an LNA (Low Noise Amplifier), LO (Local Oscillator), I/Q
mixer, polyphase lowpass filter and an IF amplifier.
The PLL generates the carrier frequency for the mixer via a full integrated synthesizer with inte-
grated low noise LC-VCO (Voltage Controlled Oscillator) and PLL-loop filter. The XTO (crystal
oscillator) generates the reference frequency f
XTO
. The integrated LC-VCO generates two times
the mixer drive frequency f
VCO
. The I/Q signals for the mixer are generated with a divide by two
circuit (f
LO
= f
VCO
/2). f
VCO
is divided by a factor of 256 and feeds into a phase frequency detector
and compared with f
XTO
. The output of the phase frequency detector is fed into an integrated
loop filter and thereby generates the control voltage for the VCO. If f
LO
is determined, f
XTO
can be
calculated using the following formula:
f
XTO
= f
LO
/128
The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal with
high current but low voltage signal, so that there is only a small voltage at the crystal oscillator
frequency at pin XTAL. According to
Figure 3-1,
the crystal should be connected to GND with a
series capacitor C
L
. The value of that capacitor is recommended by the crystal supplier. Due to a
somewhat inductive impedance at steady state oscillation and some PCB parasitics a lower
value of C
L
is normally necessary.
The value of C
L
should be optimized for the individual board layout to achieve the exact value of
f
XTO
(the best way is to use a crystal with known load resonance frequency to find the right value
for this capacitor) and hereby of f
LO
. When designing the system in terms of receiving bandwidth
and local oscillator accuracy, the accuracy of the crystal and the XTO must be considered.
If a crystal with ±30 ppm adjustment tolerance at 25°C, ±50 ppm over temperature –40°C to
+105°C, ±10 ppm of total aging and a CM (motional capacitance) of 7 fF is used, an additional
XTO pulling of ±30 ppm has to be added.
The resulting total LO tolerance of ±120 ppm agrees with the receiving bandwidth specification
of the 600 kHz version of ATA5760/ATA5761 if the T5750 has also a total LO tolerance of
±120 ppm.
For the ATA5760N3 crystals with ±55 ppm total tolerance are needed for receiver and transmit-
ter to cope with the reduced IF-bandwidth.
Figure 3-1.
XTO Peripherals
V
S
DVCC
C
L
XTAL
NC
TEST 3
TEST 2
4
ATA5760/ATA5761
4896D–RKE–08/08
ATA5760/ATA5761
The nominal frequency f
LO
is determined by the RF input frequency f
RF
and the IF frequency f
IF
using the following formula (low side injection):
f
LO
= f
RF
- f
IF
To determine f
LO
, the construction of the IF filter must be considered at this point. The nominal IF
frequency is f
IF
= 950 kHz. To achieve a good accuracy of the filter corner frequencies, the filter
is tuned by the crystal frequency f
XTO
. This means that there is a fixed relation between f
IF
and
f
LO
.
f
IF
= f
LO
/915 for B
IF
= 600 kHz
f
IF
= f
LO
/878 for B
IF
= 300 kHz
The relation is designed to achieve the nominal IF frequency of
f
IF
= 950 kHz for the 868.3 MHz and B
IF
= 600 kHz version,
f
IF
= 989 kHz for the 868.3 MHz and B
IF
= 300 kHz version and
for the 915 MHz version an IF frequency of f
IF
= 1.0 MHz results.
The RF input either from an antenna or from an RF generator must be transformed to the RF
input pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The
parasitic board inductances and capacitances influence the input matching. The RF receiver
ATA5760/ATA5761 exhibits its highest sensitivity if the LNA is power matched. This makes the
matching to an SAW filter as well as to 50Ω or an antenna easier.
Figure 14-1 on page 30
shows a typical input matching network for f
RF
= 868.3 MHz to 50Ω.
Fig-
ure 14-2 on page 30
illustrates an according input matching for 868.3 MHz to an SAW. The input
matching network shown in
Figure 14-1 on page 30
is the reference network for the parameters
given in the electrical characteristics.
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4896D–RKE–08/08
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