DS2174Q+T&R datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> DS2174Q+T&R

DS2174Q+T&R: DescriptionCommunication ICs - Various Enhanced Bit Error Rate Tester (BERT); CategoryWireless rf/communication Telecom circuit; File Size259KB，24 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html; Environmental Compliance

Download Datasheet Parametric Compare View All

DS2174Q+T&R Overview

Communication ICs - Various Enhanced Bit Error Rate Tester (BERT)

DS2174Q+T&R Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Maxim
Parts packaging code	LCC
package instruction	QCCJ, LDCC44,.7SQ
Contacts	44
Reach Compliance Code	compliant
JESD-30 code	S-PQCC-J44
JESD-609 code	e3
length	16.585 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum slew rate	0.06 mA
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	16.585 mm

Preview

Download Datasheet

View All

DS2174

EBERT

www.maxim-ic.com

GENERAL DESCRIPTION

The DS2174 enhanced bit error-rate tester

(EBERT) is a software-programmable test-pattern

generator, receiver, and analyzer capable of

meeting the most stringent error-performance

requirements of digital transmission facilities. It

features bit-serial, nibble-parallel, and byte-

parallel data interfaces, and generates and

uniquely synchronizes to pseudorandom patterns

of the form 2

- 1, where n can take on values from

1 to 32, and user-defined repetitive patterns of any

length up to 512 octets.

FEATURES

Generates and detects digital patterns for

analyzing and trouble-shooting digital

communications systems

Programmable polynomial length and

feedback taps for generation of any

pseudorandom patterns up to 2

- 1; up to

32 taps can be used in the feedback path

Programmable, user-defined pattern

registers for long repetitive patterns up to

512 bytes in length

Large 48-bit count and bit error count

registers

Software-programmable bit error insertion

Fully independent transmit and receive

paths

8-bit parallel-control port

Detects polynomial test patterns in the

presence of bit error rates up to 10

-2

Programmable for serial, 4-bit parallel, or

8-bit parallel data interfaces

Serial mode clock rate is 155MHz; byte

mode is 80MHz for a net 622Mbps; OC-3

Available in 44-pin PLCC

APPLICATIONS

Routers

Channel Service Units (CSUs)

Data Service Units (DSUs)

Muxes

Switches

Digital-to-Analog Converters (DACs)

CPE Equipment

Bridges

Smart Jack

PIN CONFIGURATION

TOP VIEW

RDAT2

RDAT1

RDAT0

RCLK_EN

RCLK

VDD

ORDERING INFORMATION

PART

DS2174Q

TDAT7

TDAT6

GND

TDAT5

TDAT4

TDAT3

TDAT2

GND

RDAT3

RDAT4

RDAT5

RDAT6

RDAT7

GND

TEMP

RANGE

0°C to +70°C

-40°C to +85°C

PIN-

PACKAGE

44 PLCC

DS2174QN

DS2174

Note:

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata.

TEST

GND

VDD

TCLK

TCLK_EN

TCLKO

TDAT0

TDAT1

1 of 24

091302

DS2174

TABLE OF CONTENTS

1.1

GENERAL OPERATION

................................................................................................................4

ATTERN

ENERATION

......................................................................................................................4

1.1.1 Polynomial Generation..........................................................................................

1.1.2 Repetitive Pattern Generation

............................................................................... 4

1.2

ATTERN

YNCHRONIZATION

............................................................................................................5

1.2.1 Synchronization......................................................................................................

1.2.2 Polynomial Synchronization

.................................................................................. 5

1.2.3 Repetitive Pattern Synchronization

....................................................................... 5

1.3

1.4

1.5

1.6

1.7

3.1

3.2

3.3

3.4

3.5

4.1

6.1

6.2

RROR

ATE

(BER) C

ALCULATION

............................................................................................5

ENERATING

RRORS

.......................................................................................................................5

LOCK

ISCUSSION

...........................................................................................................................6

OWER

-U

EQUENCE

.......................................................................................................................6

ETAILED

ESCRIPTION

.............................................................................................................8

PARALLEL CONTROL INTERFACE........................................................................................10

CONTROL REGISTERS

...............................................................................................................11

ODE

ELECT

.................................................................................................................................13

TATUS

EGISTER

...........................................................................................................................15

SEUDORANDOM

ATTERN

EGISTERS

...........................................................................................15

EST

EGISTER

................................................................................................................................17

OUNT

EGISTERS

..........................................................................................................................17

RAM ACCESS

.................................................................................................................................18

NDIRECT

DDRESSING

....................................................................................................................18

DC OPERATION

............................................................................................................................19

AC TIMING CHARACTERISTICS

.............................................................................................20

ARALLEL

ORT

..............................................................................................................................20

ATA

NTERFACE

............................................................................................................................22

MECHANICAL DIMENSIONS

....................................................................................................24

1.3.1 Counters

................................................................................................................. 5

3.1.1 Error Insertion

..................................................................................................... 13

2 of 24

DS2174

LIST OF FIGURES

FIGURE 1-1. BLOCK DIAGRAM

.............................................................................................................. 6

FIGURE 6-1. READ TIMING

................................................................................................................... 20

FIGURE 6-2. WRITE TIMING..................................................................................................................

FIGURE 6-3. TRANSMIT INTERFACE TIMING...................................................................................

FIGURE 6-4. RECEIVE INTERFACE TIMING

...................................................................................... 23

LIST OF TABLES

TABLE 1-A. PIN ASSIGNMENT

............................................................................................................... 7

TABLE 2-A. REGISTER MAP

................................................................................................................. 10

TABLE 3-A. MODE SELECT...................................................................................................................

TABLE 3-B. ERROR BIT INSERTION....................................................................................................

TABLE 3-C. PSEUDORANDOM PATTERN GENERATION

............................................................... 16

TABLE 5-A. RECOMMENDED DC OPERATING CONDITIONS

....................................................... 19

TABLE 5-B. DC CHARACTERISTICS

................................................................................................... 19

TABLE 6-A. PARALLEL PORT READ TIMING

................................................................................... 20

TABLE 6-B. PARALLEL PORT WRITE TIMING..................................................................................

TABLE 6-C. TRANSMIT DATA TIMING...............................................................................................

TABLE 6-D. RECEIVE DATA TIMING..................................................................................................

3 of 24

DS2174

1. GENERAL OPERATION

1.1 Pattern Generation

1.1.1 Polynomial Generation

The DS2174 has a tap select register that can be used as a mask to tap up to 32 bits in the feedback path

of the polynomial generator. It also features a seed register that can be used to preload the polynomial

generator with a seed value. This is done on the rising edge of TL in Control Register 1.

The DS2174 generates polynomial patterns of any length up to and including 2

- 1. All of the industry-

standard polynomials can be programmed using the control registers. The polynomial is generated using a

shift register of programmable length and programmable feedback tap positions. The user has access to

all combinations of pattern length and pattern tap location to generate industry-standard polynomials or

other combinations as well. In addition, the QRSS pattern described in T1.403 is described by the

polynomial 2

– 1. This pattern has the additional requirement that “an output bit is forced to a 1

whenever the next 14 bits are 0.” Setting the QRSS bit in Control Register 1 causes the pattern generator

to enforce this rule.

1.1.2 Repetitive Pattern Generation

In addition to polynomial patterns, the DS2174 generates repetitive patterns of considerable length. The

programmer has access to 512 bytes of memory for storing pattern. The pattern length bits PL0 through

PL8, located at addresses 02h and 03h, are used to program the length of the repetitive pattern. Memory is

addressed indirectly and is used to store the pattern. Data can be sent MSB or LSB first as it appears in

the memory.

Repetitive patterns can include simple patterns such as 3 in 24, but the additional memory can be used to

store patterns such as DDS-n patterns or T1-n patterns. Repetitive patterns are stored in increments of 8

bits. To generate a repetitive pattern that is 12 bits long (3 nibbles), the pattern is written twice such that

the pattern is 24 bits long (3 bytes), and repeats twice in memory. The same is true when the device is

used in serial mode: a 5-bit pattern is written to memory 5 times. For example,

To generate a 00001 pattern at the serial output, write these bytes to memory:

RAM ADDRESS

00h

01h

02h

03h

04h

BINARY CODE

00010000

01000010

00001000

00100001

10000100

HEX CODE

10h

42h

08h

21h

84h

4 of 24

DS2174

1.2 Pattern Synchronization

1.2.1 Synchronization

The receiver synchronizes to the same pattern that is being transmitted. The pattern must be error free

when the synchronizer is online. Once synchronized, an error density of 6 bits in 64 causes the receiver to

declare loss-of-pattern sync, set the RLOS bit, and the synchronizer comes back online.

1.2.2 Polynomial Synchronization

Synchronization to polynomial patterns take 50 + n clock cycles (14 + n in nibble mode, 8 + n in byte

mode), where n is the exponent in the polynomial that describes the pattern. Once synchronized, any bit

that does not match the polynomial is counted as a bit error.

1.2.3 Repetitive Pattern Synchronization

Synchronization to repetitive patterns can take several complete repetitions of the entire pattern. The

actual sync time depends on the nature of the pattern and the location of the synchronization pointer.

Errors that occur during synchronization could affect the sync time; at least one complete error-free

repetition must be received before synchronization is declared. Once synchronized, any bit that does not

match the pattern that is programmed in the on-board RAM is counted as a bit error.

1.3 Bit Error Rate (BER) Calculation

1.3.1 Counters

The bit counter is active at all times. Once synchronized, the error counters come online. The receiver has

large 48-bit count registers. These counters accumulate for 50,640 hours at the T1 line rate, 1.544MHz,

and 38,170 hours at the E1 line rate, 2.048MHz. At higher clock rates, the counters saturate quicker, but

at the T3 line rate, the counter still runs for almost 1500 hours, and at 155MHz it runs for 504 hours.

To accumulate BER data, the user toggles the LC bit at T = 0. This clears the accumulators and loads the

contents into the count registers. At T = 0, these results should be ignored. At this point, the device is

counting bits and bit errors. At the end of the specified time interval, the user toggles the LC bit again and

reads the count registers. These are the valid results used to calculate a bit error rate. Remember, the bit

counter is really counting clocks, so in nibble and byte modes the bit counter value needs to be multiplied

by 4 or 8 to get the correct bit count. For longer integration periods, the results of multiple read cycles

have to be accumulated in software.

1.4 Generating Errors

Through Control Register 2, the user can intentionally inject a particular error rate into the transmitted

data stream. Injecting errors allows users to stress communication links and to check the functionality of

error monitoring equipment along the path.

5 of 24

DS2174Q+T&R Related Products

	DS2174Q+T&R	DS2174QN-TR	DS2174Q+	DS2174QN+	DS2174Q	DS2174QN/T&R	DS2174Q/T&R
Description	Communication ICs - Various Enhanced Bit Error Rate Tester (BERT)	Communication ICs - Various Enhanced Bit Error Rate Tester (BERT)	Communication ICs - Various Enhanced Bit Error Rate Tester (BERT)	Communication ICs - Various Enhanced Bit Error Rate Tester (BERT)	Communication ICs - Various Enhanced Bit Error Rate Tester (BERT)	Communication ICs - Various ENHANCED BIT ERROR RATE TESTER IND	Communication ICs - Various ENHANCED BIT ERROR RATE TESTER COMM
Is it lead-free?	Lead free	-	Lead free	Lead free	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	conform to	-	conform to	conform to	incompatible	incompatible	incompatible
Maker	Maxim	-	Maxim	Maxim	Maxim	Maxim	Maxim
Parts packaging code	LCC	-	LCC	LCC	LCC	LCC	LCC
package instruction	QCCJ, LDCC44,.7SQ	-	QCCJ, LDCC44,.7SQ	QCCJ, LDCC44,.7SQ	PLASTIC, LCC-44	PLASTIC, LCC-44	PLASTIC, LCC-44
Contacts	44	-	44	44	44	44	44
Reach Compliance Code	compliant	-	compliant	compliant	not_compliant	not_compliant	not_compliant
JESD-30 code	S-PQCC-J44	-	S-PQCC-J44	S-PQCC-J44	S-PQCC-J44	S-PQCC-J44	S-PQCC-J44
JESD-609 code	e3	-	e3	e3	e0	e0	e0
length	16.585 mm	-	16.585 mm	16.585 mm	16.585 mm	16.585 mm	16.585 mm
Humidity sensitivity level	3	-	3	3	3	3	3
Number of functions	1	-	1	1	1	1	1
Number of terminals	44	-	44	44	44	44	44
Maximum operating temperature	70 °C	-	70 °C	85 °C	70 °C	85 °C	70 °C
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	-	QCCJ	QCCJ	QCCJ	QCCJ	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ	-	LDCC44,.7SQ	LDCC44,.7SQ	LDCC44,.7SQ	LDCC44,.7SQ	LDCC44,.7SQ
Package shape	SQUARE	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER	-	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260	-	260	260	245	245	245
power supply	3.3 V	-	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	-	4.57 mm	4.57 mm	4.57 mm	4.57 mm	4.57 mm
Maximum slew rate	0.06 mA	-	0.06 mA	0.06 mA	0.06 mA	0.06 mA	0.06 mA
Nominal supply voltage	3.3 V	-	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	-	YES	YES	YES	YES	YES
Telecom integrated circuit types	TELECOM CIRCUIT	-	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT
Temperature level	COMMERCIAL	-	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	-	Matte Tin (Sn)	Matte Tin (Sn)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	J BEND	-	J BEND	J BEND	J BEND	J BEND	J BEND
Terminal pitch	1.27 mm	-	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	QUAD	-	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	16.585 mm	-	16.585 mm	16.585 mm	16.585 mm	16.585 mm	16.585 mm

Recommended Resources

base amplitude modulation circuit

Two water quality detection circuits

Same polarity drive circuit

800Hz oscillator circuit

20-bit optical receiving circuit

Computer motherboard circuit diagram 815 5_08

How to Repair a CRT Monitor with Scan Line Problems: I have an LG CRT monitor, bought in 2002, 17 flat screen, and now it has a problem, there is always a horizontal tilted light gray scan line, about 4 cm wide, the background is basically pure white, a...; xiyuan98 Embedded System

Is there a suitable chip/solution for converting 24V to positive and negative 15V?: 1. Requirements: 24V to +/- 15V chip/solution, load capacity of about 0.5A, maximum input voltage 60V 2. Origin of the problem: The 24V battery is the power supply, and I want to directly convert it i...; 向阳xl Power technology

Received IT activity gift thermos cup: [size=5]I received a thermos cup, it is well made and has TI's logo, it looks high-end[/size] [size=5]I saw that the thermos cups given away in the forum recently are all imported brands[/size] [size=...; littleshrimp Talking

Simulation of MCU control 18B20, can't debug it, please help: When debugging the 18B20 program separately, I can see the changes in high and low levels. When debugging the digital tube display program separately, it can also display correctly, but there is no ch...; shijizai 51mcu

What are the advantages of using the frequency adjusted by the internal DCO of 430 compared with an external crystal oscillator?: What are the advantages of using the frequency adjusted by the internal DCO of 430 compared with an external crystal oscillator?...; allkity Microcontroller MCU

Designed for students: throw out all the questions in your mind! Let's learn cool summer courses at EEWORLD! (9 lessons updated): Summer vacation is here. I believe many students are studying in school, preparing for electronic competitions, or working on projects with teachers. In this process, you may encounter various directi...; EEWORLD社区 Integrated technical exchanges

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components