IS42S81600D
IS42S16800D
16Meg x 8, 8Meg x16
128-MBIT SYNCHRONOUS DRAM
JULY 2008
FEATURES
• Clock frequency: 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply
IS42S81600D
IS42S16800D
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable
CAS
latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Industrial Temperature Availability
• Lead-free Availability
V
DDQ
V
DD
3.3V 3.3V
3.3V 3.3V
OVERVIEW
ISSI
's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock
input.The 128Mb SDRAM is organized as follows.
IS42S81600D
4M x8x4 Banks
54-pin TSOPII
IS42S16800D
2M x16x4 Banks
54-pin TSOPII
54-ball BGA
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS
Latency = 3
CAS
Latency = 2
Clk Frequency
CAS
Latency = 3
CAS
Latency = 2
Access Time from Clock
CAS
Latency = 3
CAS
Latency = 2
-6
6
8
166
125
5.4
6.5
-7
7
10
143
100
5.4
6.5
-75E
—
7.5
—
133
—
6.5
Unit
ns
ns
Mhz
Mhz
ns
ns
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
1
IS42S81600D,
IS42S16800D
DEVICE OVERVIEW
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V V
DD
and 3.3V V
DDQ
memory systems containing 134,217,728
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 33,554,432-bit bank is orga-
nized as 4,096 rows by 512 columns by 16 bits or 4,096 rows
by 1,024 columns by 8 bits.
The 128Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All
inputs and outputs are LVTTL compatible.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tion enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting at
a selected location and continuing for a programmed num-
ber of locations in a programmed sequence. The registra-
tion of an ACTIVE command begins accesses, followed by
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Programmable READ or WRITE burst lengths consist of 1,
2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONLY)
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
16
16
2
MODE
REGISTER
12
REFRESH
CONTROLLER
DQ 0-15
SELF
REFRESH
CONTROLLER
A10
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
12
DATA OUT
BUFFER
16
16
V
DD
/V
DDQ
V
ss
/V
ss
Q
REFRESH
COUNTER
4096
4096
4096
4096
ROW DECODER
MULTIPLEXER
MEMORY CELL
ARRAY
12
ROW
ADDRESS
LATCH
12
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
9
512
(x 16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
MCU
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