DATASHEET
ACTS161MS
Radiation Hardened 4-Bit Synchronous Counter
FN4095
Rev.0.00
January 1996
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-96716 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/
Bit/Day (Typ)
• SEU LET Threshold>100 MEV-cm
2
/mg
• Dose Rate Upset>10
11
RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability>10
12
RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range-55
o
C to +125
o
C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current
1A at VOL, VOH
• Fast Propagation Delay25ns (Max), 16ns (Typ)
Pinouts
16 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835, DESIGNATOR CDIP2-T16,
LEAD FINISH C
TOP VIEW
MR 1
CP 2
P0 3
P1 4
P2 5
P3 6
PE 7
GND 8
16 VCC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 TE
9 SPE
16 PIN CERAMIC FLATPACK
MIL-STD-1835, DESIGNATOR CDFP4-F16,
LEAD FINISH C
TOP VIEW
MR
CP
P0
P1
P2
P3
PE
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
TC
Q0
Q1
Q2
Q3
TE
SPE
Description
The Intersil ACTS161MS is a Radiation Hardened 4-Bit Binary Syn-
chronous Counter, featuring asynchronous reset and load ahead
carry logic. The MR is an active low master reset. SPE is an active
low Synchronous Parallel Enable which disables counting and
allows data at the preset inputs (P0 - P3) to load the counter. CP is
the positive edge clock. TC is the terminal count or carry output.
Both TE and PE must be high for counting to occur, but are irrele-
vant to loading. TE low will keep TC low.
The ACTS161MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of a
radiation hardened, high-speed, CMOS/SOS Logic family.
The ACTS161MS is supplied in a 16 lead Ceramic Flatpack
(K suffix) or a Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
5962F9671601VEC
5962F9671601VXC
ACTS161D/Sample
ACTS161K/Sample
ACTS161HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
FN4095 Rev.0.00
January 1996
Page 1 of 4
ACTS161MS
Functional Diagram
P0
3
P1
4
P2
5
P3
6
Q0 Q1
Q2 Q3
PE
7
TE
10
TE
TE
SPE
9
MR
1
P
T0
MR
D0 Q0
P
T1
MR
CP
D1 Q1
P
T2
MR
CP
D2 Q2
P
T3
MR
CP
D3 Q3
GND
2
CP
CP
14
Q0
Q1
13
Q2
12
Q3
11
TC
15
TRUTH TABLE
INPUTS
OPERATING MODE
Reset (Clear)
Parallel Load
MR
L
H
H
Count
Inhibit
H
H
H
X
X
CP
X
PE
X
X
X
h
I (Note 2)
X
TE
X
X
X
h
X
I (Note 2)
SPE
X
I
I
h (Note 3)
h (Note 3)
h (Note 3)
P
N
X
I
h
X
X
X
OUTPUTS
Q
N
L
L
H
count
q
N
q
N
TC
L
L
(Note 1)
(Note 1)
(Note 1)
L
H = High Steady State, L = Low Steady State, h = High voltage level one setup time prior to the Low-to-High clock transition, I = Low volt-
age level one setup time prior to the Low-to-High clock transition, X = Don’t Care,q = Lower case letters indicate the state of the referenced
output prior to the Low-to-High clock transition,
= Low-to-High Transition.
NOTES:
1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH).
2. The High-to-Low transition of PE or TE should only occur while CP is High for conventional operation.
3. The Low-to-High transition of SPE should only occur while CP is High for conventional operation.
FN4095 Rev.0.00
January 1996
Page 2 of 4
ACTS161MS
© Copyright Intersil Americas LLC 1999. All Rights Reserved.
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For additional products, see
www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at
www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see
www.intersil.com
FN4095 Rev.0.00
January 1996
Page 4 of 4
DSP and ARM Processors
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