14-Bit, 80 MSPS, A/D Converter
AD9444
FEATURES
80 MSPS guaranteed sampling rate
100 dB two-tone SFDR with 69.3 MHz and 70.3 MHz
73.1 dB SNR with 70 MHz input
97 dBc SFDR with 70 MHz input
Excellent linearity
DNL = ±0.4 LSB typical
INL = ±0.6 LSB typical
1.2 W power dissipation
3.3 V and 5 V supply operation
2.0 V p-p differential full-scale input
LVDS outputs (ANSI-644 compatible)
Data format select
Output clock available
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2
DRGND DRVDD
DFS
DCS MODE
BUFFER
VIN+
VIN–
T/H
PIPELINE
ADC
14
CMOS
OR
LVDS
OUTPUT
STAGING
2
28
D13–D0
2
DCO
REF
05089-001
AD9444
OUTPUT MODE
OR
CLK+
CLK–
CLOCK
AND TIMING
MANAGEMENT
VREF SENSE REFT REFB
Figure 1.
APPLICATIONS
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar, infared imaging
Communications instrumentation
Optional features allow users to implement various selectable
operating conditions, including data format select and output
data mode.
The AD9444 is available in a 100-lead surface-mount plastic
package (100-lead TQFP/EP) specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. High performance: Outstanding SFDR performance for mul-
ticarrier, multimode 3G and 4G cellular base station
receivers.
2. Ease of use: On-chip reference and track-and-hold. An
output clock simplifies data capture.
3. Packaged in a Pb-free, 100-lead TQFP/EP.
4. Clock DCS maintains overall ADC performance over a wide
range of clock pulse widths.
5. OR (out-of-range) outputs indicate when the signal is beyond
the selected input range.
GENERAL DESCRIPTION
The AD9444 is a 14-bit monolithic, sampling analog-to-digital
converter (ADC) with an on-chip, track-and-hold circuit and is
optimized for power, small size, and ease of use. The product
operates at up to an 80 MSPS conversion rate and is optimized
for multicarrier, multimode receivers, such as those found in
cellular infrastructure equipment.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are LVDS-compatible (ANSI-
644) or CMOS-compatible and include the means to reduce
the overall current needed for short trace distances.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD9444
TABLE OF CONTENTS
DC Specifications ............................................................................. 3
AC Specifications.............................................................................. 4
Digital Specifications........................................................................ 5
Switching Specifications .................................................................. 6
Explanation of Test Levels........................................................... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Definitions of Specifications ........................................................... 9
Pin Configurations and Function Descriptions ......................... 10
Equivalent Circuits ......................................................................... 14
Typical Performance Characteristics ........................................... 15
Theory of Operation ...................................................................... 20
Analog Input and Reference Overview ................................... 20
Clock Input Considerations...................................................... 22
Power Considerations................................................................ 23
Digital Outputs ........................................................................... 23
Timing ......................................................................................... 23
Operational Mode Selection ..................................................... 23
Evaluation Board ........................................................................ 24
LVDS Evaluation Board Schematics ........................................ 25
LVDS Mode Evaluation Board Bill of Materials (BOM) ...... 30
CMOS Evaluation Board Schematics ...................................... 32
CMOS Mode Evaluation Board Bill of Materials (BOM)..... 37
Outline Dimensions ....................................................................... 39
Ordering Guide .......................................................................... 39
REVISION HISTORY
10/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
AD9444
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed
reference (1.0 V mode), A
IN
= −0.5 dBFS, DCS on, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
1
Differential Nonlinearity (DNL)
2
Integral Nonlinearity (INL)
2
TEMPERATURE DRIFT
Offset Error
Gain Error
VOLTAGE REFERENCE
Output Voltage
1
Load Regulation @ 1.0 mA
Reference Input Current (External 1.0 V Reference)
INPUT REFERRED NOISE
ANALOG INPUT
Input Span
Input Common-Mode Voltage
Input Resistance
3
Input Capacitance
3
POWER SUPPLIES
Supply Voltage
AVDD1
AVDD2
DRVDD—LVDS Outputs
DRVDD—CMOS Outputs
Supply Current
AVDD1
AVDD2
2
IDRVDD
2
—LVDS Outputs
IDRVDD
2
—CMOS Outputs
PSRR
Offset
Gain
POWER CONSUMPTION
DC Input—LVDS Outputs
DC Input—CMOS Outputs
Sine Wave Input
2
—LVDS Outputs
Sine Wave Input
2
—CMOS Outputs
Temp
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Test Level
VI
VI
VI
VI
VI
I
VI
V
V
VI
V
VI
V
V
V
V
V
0.87
Min
AD9444BSVZ-80
Typ
Max
14
Guaranteed
±0.3
±0.4
±0.4
±0.6
Unit
Bits
6
−3.0
−0.8
−1.3
−1.7
6
+3.0
+0.8
+1.3
+1.7
mV
% FSR
LSB
LSB
LSB
µV/°C
%FS/°C
12
0.002
1.0
±2
80
1.0
2
3.5
1
2.5
1.13
125
V
mV
µA
LSB rms
V p-p
V
kΩ
pF
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
VI
VI
VI
V
V
V
VI
V
VI
V
3.14
4.75
3.0
3.0
3.3
5.0
3.3
217
71
55
12
1
0.2
1.21
1.07
1.25
1.11
3.46
5.25
3.6
3.6
240
80
62
V
V
V
V
mA
mA
mA
mA
mV/V
%/V
1.4
W
W
W
W
1
2
The internal voltage reference is trimmed at final test to minimize the gain error of the AD9444.
Measured at the maximum clock rate, f
IN
= 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
3
Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input
structure.
Rev. 0 | Page 3 of 40
AD9444
AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed
reference (1.0 V mode), A
IN
= −0.5 dBFS, DCS on, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE-RATIO (SNR)
f
IN
= 10 MHz
f
IN
= 35 MHz
f
IN
= 70 MHz
f
IN
= 100 MHz
SIGNAL-TO-NOISE-AND DISTORTION (SINAD)
f
IN
= 10 MHz
f
IN
= 35 MHz
f
IN
= 70 MHz
f
IN
= 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 10 MHz
f
IN
= 35 MHz
f
IN
= 70 MHz
f
IN
= 100 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
IN
= 10 MHz
f
IN
= 35 MHz
f
IN
= 70 MHz
f
IN
= 100 MHz
WORST HARMONIC, SECOND OR THIRD
f
IN
= 10 MHz
f
IN
= 35 MHz
f
IN
= 70 MHz
f
IN
= 100 MHz
WORST SPUR EXCLUDING SECOND OR HARMONICS
f
IN
= 10 MHz
f
IN
= 35 MHz
f
IN
= 70 MHz
f
IN
= 100 MHz
TWO-TONE SFDR
f
IN
= 10.8 MHz @ −7 dBFS, 9.8 MHz @ −7 dBFS
f
IN
= 70.3 MHz @ −7 dBFS, 69.3 MHz @ −7 dBFS
ANALOG BANDWIDTH
Temp
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
Test Level
IV
IV
I
IV
IV
IV
V
IV
IV
I
IV
IV
IV
V
V
V
V
V
IV
IV
I
IV
IV
IV
V
IV
IV
I
IV
IV
IV
V
IV
IV
I
IV
IV
IV
V
V
V
V
91
87
91
87
90
87
Min
73.0
72.7
72.4
72.3
72.3
72.0
AD9444BSVZ-80
Typ
Max
74.0
73.7
73.1
72.3
73.0
72.7
72.4
72.2
72.2
72.0
74.0
73.7
73.1
72.3
12.1
12.0
11.9
11.8
97
97
97
96
−97
−97
−97
−96
−102
−103
−102
−99
−102
−100
650
−93
−93
−93
−93
−93
−93
−91
−87
−91
−87
−90
−87
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
MHz
Rev. 0 | Page 4 of 40
AD9444
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, R
LVDSBIAS
= 3.74 kΩ, unless otherwise noted.
Table 3.
Parameter
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS—CMOS Mode (D0 to D13, OTR)
1
DRVDD = 3.3 V
High Level Output Voltage
Low Level Output Voltage
DIGITAL OUTPUT BITS LVDS Mode (D0 to D13, OTR)
V
OD
Differential Output Voltage
2
V
OS
Output Offset Voltage
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage
Common-Mode Voltage
Differential Input Resistance
Differential Input Capacitance
Temp
Full
Full
Full
Full
Full
Test Level
IV
IV
VI
VI
V
AD9444BSVZ-80
Min
Typ
Max
2.0
0.8
+200
+10
2
Unit
V
V
µA
µA
pF
−10
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
VI
VI
IV
VI
V
V
3.25
0.2
247
1.125
0.2
1.3
8
545
1.375
V
V
mV
V
V
V
kΩ
pF
1.5
10
4
1.6
12
1
2
Output voltage levels measured with 5 pF load on each output.
LVDS R
TERM
= 100 Ω.
Rev. 0 | Page 5 of 40
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