73K321L
CCITT V.23, V.21
Single-Chip Modem
April 2000
DESCRIPTION
The 73K321L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a CCITT V.23 and V.21 compatible
modem, capable of 0-300 bit/s full-duplex or 0-1200
bit/s half-duplex operation over dial-up telephone
lines. The 73K321L provides 1200 bit/s operation in
V.23 mode and 300 bit/s in V.21 mode. The
73K321L also can both detect and generate the
2100 Hz answer tone needed for call initiation. The
73K321L integrates analog, digital, and switched-
capacitor array functions on a single substrate,
offering excellent performance and a high level of
functional integration in a single 28-pin DIP or PLCC
package. The 73K321L operates from a single +5V
supply with very low power consumption.
The
73K321L
includes
the
FSK
modulator/demodulator functions, call progress and
handshake tone monitor test modes, and a tone
generator capable of producing DTMF, answer,
calling tones. The 73K321L is designed to appear to
the systems designer as a microprocessor
peripheral, and will easily interface with popular one-
chip microprocessors (80C51 typical) for control of
modem functions through its 8-bit multiplexed
address/data bus or via an optional serial control
bus. An ALE control line simplifies address
demultiplexing.
Data
communications
occurs
through a separate serial port only.
(continued)
FEATURES
•
•
One-chip CCITT V.23 and V.21 standard
compatible modem data pump
Full-duplex operation at 0-300 bit/s (V.21) or
0-1200 bit/s ( .23) forward channel with or
V
without 0-75 bits/s back channel
Full Duplex 0-1200 bit/s (V.23) in 4-wire mode
Pin and software compatible with other TDK
Semiconductor Corporation K-Series 1-chip
modems
Interfaces directly with standard
processors (8048, 80C51 typical)
Serial port for data transfer
Call progress, carrier, precise answer tone
(2100 Hz), calling tone (1300 Hz) and FSK
mark detectors
DTMF generator
Test modes available: ALB, DL, RDL, Mark,
Space, Alternating bit patterns
Precise automatic gain control allows 45 dB
dynamic range
CMOS
technology
for
low
power
consumption using 60 mW @ 5V from a
single power supply
micro-
•
•
•
•
•
•
•
•
•
BLOCK DIAGRAM
DATA
BUS
BUFFER
DTMF &
TONE
GENERATORS
AD0-AD7
8-BIT
BUS
FOR
FSK
MODULATOR/
DEMODULATOR
RD
WR
ALE
CS
RESET
READ
WRITE
CONTROL
LOGIC
CONTROL
AND
STATUS
TRANSMIT
FILTER
RECEIVE
FILTER
TXA
RXA
INT
STATUS
AND
CONTROL
LOGIC
TXD
RXD
SERIAL
PORT
FOR
DATA
TESTS:
ALB,DLB
RDLB
PATTERNS
SMART
DIALING
&
DETECT
FUNCTIONS
CLOCK
GENERATOR
POWER
RXCLK
TXCLK
CLK
EXCLK
GND
XTL1
XTL2
VREF
VDD
ISET
73K321L
CCITT V.23, V.21
Single-Chip
DESCRIPTION
(continued)
The 73K321L is ideal for either free standing or
integral system modem applications where multi-
standard data communications over the 2-wire
switched telephone network is desired. Typical uses
include videotex terminals, low-cost integral modems
and built-in diagnostics for office automation or
industrial control systems. The 73K321L’s high
functionality, low power consumption and efficient
packaging simplify design requirements and increase
system reliability in these applications. A complete
modem requires only the addition of the phone line
interface, a control microprocessor, and RS-232 level
converter for a typical system. The 73K321L is part of
TDK Semiconductor's K-Series family of pin and
function compatible single-chip modem products.
These devices allow systems to be configured for
higher speeds and Bell or CCITT operation with only
a single component change.
OPERATION
FSK MODULATOR/DEMODULATOR
The FSK modulator produces a frequency
modulated analog output signal using two discrete
frequencies to represent the binary data. V.21 mode
uses 980 and 1180 Hz (originate, mark and space)
or 1650 and 1850 Hz (answer, mark and space).
V.23 mode uses 1300 and 2100 Hz for the main
channel and 390 and 450 Hz for the back channel.
The modulation rate of the back channel is up to 75
baud. Demodulation involves detecting the received
frequencies and decoding them into the appropriate
binary value.
PASSBAND FILTERS AND EQUALIZERS
High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay
equalization and rejection of out-of-band signals in the
receive channel. Amplitude and phase equalization
are necessary to compensate for distortion of the
transmission line and to reduce intersymbol
interference in the bandlimited receive signal.
AGC
The automatic gain control maintains a signal level
at the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping and provides a total
receiver dynamic range of >45 dB.
PARALLEL BUS INTERFACE
Four 8-bit registers are provided for control, option
select and status monitoring. These registers are
addressed with the AD0, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a
control microprocessor as four consecutive memory
locations. Two control registers and the tone register
are read/write memory. The detect register is read
only and cannot be modified except by modem
response to monitored parameters.
SERIAL CONTROL INTERFACE
The Serial Command mode allows access to the
73K321L control and status registers via a serial
command port. In this mode the AD0, AD1 and AD2
lines provide register addresses for data passed
through the data pin under control of the
RD
and
WR
lines. A read operation is initiated when the
RD
line is taken low. The first bit is available after RD is
brought low and the next seven cycles of EXCLK will
then transfer out seven bits of the selected address
location LSB first. A write takes place by shifting in
eight bits of data LSB first for eight consecutive
cycles of EXCLK.
WR
is then pulsed low and data
transferred into the selected register occurs on the
rising edge of
WR.
SPECIAL DETECT CIRCUITRY
The special detect circuitry monitors the received
analog signal to determine status or presence of
carrier, answer tone and weak received signal (long
loop condition). Special tones such as FSK marking
and the 1300 Hz calling tone are also detected. A
highly frequency selective call progress detector
provides adequate discrimination to accurately
detect European call progress signals.
DTMF GENERATOR
The DTMF generator will output one of 16 standard
tone-pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone
register. Dialing is initiated when the DTMF mode is
selected using the tone register and the transmit
enable (CR0 bit D1) is changed from 0 to 1.
2
73K321L
CCITT V.23, V.21
Single-Chip Modem
PIN DESCRIPTION
POWER
NAME
GND
VDD
VREF
ISET
PLCC/DIP
PIN NUMBER
28
15
26
24
TYPE
I
I
O
I
DESCRIPTION
System Ground.
Power supply input, 5V ±10%. Bypass with 0.1 and 22 µF capacitors
to GND.
An internally generated reference voltage. Bypass with 0.1 µF
capacitor to GND.
Chip current reference. Sets bias current for op-amps. The chip
current is set by connecting this pin to VDD through a 2 MΩ resistor.
ISET should be bypassed to GND with a 0.1µF capacitor.
PARALLEL MICROPROCESSOR CONTROL INTERFACE
ALE
AD0-AD7
CS
12
4-11
20
I
I/O
I
Address latch enable. The falling edge of ALE latches the address on
AD0-AD2 and the chip select on
CS.
Address/data bus. These bidirectional tri-state multi-plexed lines carry
information to and from the internal registers.
Chip select. A low during the falling edge of ALE on this pin allows a
read cycle or a write cycle to occur. AD0-AD7 will not be driven and
no registers will be written if
CS
(latched) is not active. The state of
CS
is latched on the falling edge of ALE.
Output clock. This pin is the output of the crystal oscillator frequency
only in the 73K321.
Interrupt. This open drain output signal is used to inform the
processor that a detect flag has occurred. The processor must then
read the detect register to determine which detect triggered the
interrupt.
INT
will stay low until the processor reads the detect register
or does a full reset.
Read. A low requests a read of the 73K321L internal registers. Data
cannot be output unless both
RD
and the latched
CS
are active or
low.
Reset. An active high signal high on this pin will put the chip into an
inactive state. All control register bits (CR0, CR1, Tone) will be reset.
The output of the CLK pin will be set to the crystal frequency. An
internal pull down resistor permits power on reset using a capacitor to
VDD.
CLK
INT
1
17
O
O
RD
14
I
RESET
25
I
3
73K321L
CCITT V.23, V.21
Single-Chip
PARALLEL MICROPROCESSOR CONTROL INTERFACE
(continued)
NAME
WR
PLCC/DIP
PIN NUMBER
13
TYPE
I
DESCRIPTION
Write. A low on this informs the 73K321L that data is available on
AD0-AD7 for writing into an internal register. Data is latched on the
rising edge of
WR.
No data is written unless both
WR
and the latched
CS
are low.
SERIAL MICROPROCESSOR CONTROL INTERFACE
AD0-AD2
DATA (AD7)
4-6
11
I
I/O
Register Address Selection. These lines carry register addresses and
should be valid during any read or write operation.
Serial Control Data. Data for a read/write operation is clocked in or
out on the falling edge of the EXCLK pin. The direction of data flow is
controlled by the
RD
pin.
RD
low outputs data.
RD
high inputs data.
Read. A low on this input informs the 73K321L that data or status
information is being read by the processor. The falling edge of the
RD
signal will initiate a read from the addressed register. The
RD
signal must continue for eight falling edges of EXCLK in order to read
all eight bits of the referenced register. Read data is provided LSB
first. Data will not be output unless the
RD
signal is active.
Write. A low on this input informs the 73K321L that data or status
information has been shifted in through the DATA pin and is available
for writing to an internal register. The normal procedure for a write is
to shift in data LSB first on the DATA pin for eight consecutive falling
edges of EXCLK and then to pulse
WR
low. Data is written on the
rising edge of
WR.
RD
14
I
WR
13
I
NOTE:
The Serial Control mode is provided by tying ALE high and
CS
low. In this configuration AD7 becomes
DATA and AD0, AD1 and AD2 become the address only. See the Serial Control Timing diagrams on
page 18
4
73K321L
CCITT V.23, V.21
Single-Chip Modem
DTE USER INTERFACE
NAME
EXCLK
RXCLK
RXD
PLCC/DIP
PIN NUMBER
19
23
22
TYPE
I
O
O/
Weak
Pull-up
O
DESCRIPTION
External Clock. Used for serial control interface to clock control data
in or out of the 73K321L.
Receive Clock. A clock which is 16 x1200, or 16 x 75 in V.23 mode,
or 16 x 300 baud data rate is output in V.21.
Received Digital Data Output. Serial receive data is available on this
pin. The data is always valid on the rising edge of RXCLK when in
Synchronous mode. RXD will output constant marks if no carrier is
detected.
Transmit Clock. TXCLK is always active. In V.23 mode the output is
either a 16 x 1200 baud clock or 16 x 75 baud, in V.21 mode the clock
is 16 x 300 baud.
Transmit Digital Data Input. Serial data for transmission is input on
this pin. In Asynchronous modes (1200 or 300 baud) no clocking is
necessary.
TXCLK
18
TXD
21
I
ANALOG INTERFACE AND OSCILLATOR
RXA
TXA
XTL1
XTL2
27
16
2
3
I
O
I
I
Received modulated analog signal input from the phone line.
Transmit analog output to the phone line.
These pins are for the internal crystal oscillator requiring an 11.0592
MHz Parallel mode crystal and two load capacitors to Ground. XTL2
can also be driven from an external clock.
5
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