DS1086L
3.3V Spread-Spectrum EconOscillator
General Description
The DS1086L EconOscillator™ is a 3.3V programmable
clock generator that produces a spread-spectrum
(dithered) square-wave output of frequencies from
130kHz to 66.6MHz. The selectable dithered output
reduces radiated-emission peaks by dithering the fre-
quency 0.5%,1%, 2%, 4%, or 8% below the pro-
grammed frequency. The DS1086L has a power-down
mode and an output-enable control for power-sensitive
applications. All the device settings are stored in non-
volatile (NV) EEPROM memory allowing it to operate in
stand-alone applications.
Features
♦
User-Programmable Square-Wave Generator
♦
Frequencies Programmable from 130kHz to
66.6MHz
♦
0.5%, 1%, 2%, 4%, or 8% Selectable Dithered
Output
♦
Adjustable Dither Rate
♦
Glitchless Output-Enable Control
♦
2-Wire Serial Interface
♦
Nonvolatile Settings
♦
2.7V to 3.6V Supply
♦
No External Timing Components Required
♦
Power-Down Mode
♦
5kHz Master Frequency Step Size
♦
EMI Reduction
♦
Industrial Temperature Range: -40°C to +85°C
Applications
Printers
Copiers
PCs
Computer Peripherals
Cell Phones
Cable Modems
Ordering Information
PART
DS1086LU
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
8
μSOP
(118 mils)
-40°C to +85°C
DS1086LU+
8
μSOP
(118 mils)
Note:
Contact the factory for custom settings.
+Denotes
a lead(Pb)-free/RoHS-compliant package.
Typical Operating Circuit
DITHERED 130kHz TO
66.6MHz OUTPUT
V
CC
N.C.
OUT
SPRD
V
CC
GND
DECOUPLING CAPACITORS
(0.1μF and 0.01μF)
*SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086L NEVER NEEDS
TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING.
SCL*
V
CC
Pin Configuration
TOP VIEW
μP
XTL1/OSC1
XTL2/OSC2
OUT 1
SPRD
V
CC
2
3
8
SCL
SDA
PDN
OE
DS1086L
SDA*
PDN
OE
DS1086L
7
6
5
GND 4
µSOP
EconOscillator is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6226; Rev 2; 3/12
DS1086L
3.3V Spread-Spectrum EconOscillator
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V
CC
Relative to Ground ..........-0.5V to +6.0V
Voltage Range on SPRD,
PDN,
OE, SDA, and SCL
Relative to Ground* ..................................-0.5 to (V
CC
+ 0.5V)
Continuous Power Dissipation (T
A
= +70°C)
μSOP (derate 4.5mW/°C above +70°C)........................362mW
Operating Temperature Range ...........................-40°C to +85°C
*This
voltage must not exceed 6.0V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Programming Temperature Range .........................0°C to +70°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-55°C to +150°C
Soldering Temperature (reflow)
Lead(Pb)-free................................................................+260°C
Containing lead(Pb) ......................................................+240°C
RECOMMENDED DC OPERATING CONDITIONS
(V
CC
= 2.7V to 3.6V, T
A
= -40°C to +85°C.)
PARAMETER
Supply Voltage
High-Level Input Voltage
(SDA, SCL, SPRD,
PDN,
OE)
Low-Level Input Voltage
(SDA, SCL SPRD,
PDN,
OE)
SYMBOL
V
CC
V
IH
V
IL
(Note 1)
CONDITIONS
MIN
2.7
0.7 x
V
CC
-0.3
TYP
3.3
MAX
3.6
V
CC
+
0.3
0.3 x
V
CC
UNITS
V
V
V
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V to 3.6V, T
A
= -40°C to +85°C.)
PARAMETER
High-Level Output Voltage (OUT)
Low-Level Output Voltage (OUT)
Low-Level Output Voltage (SDA)
High-Level Input Current
Low-Level Input Current
Supply Current (Active)
Standby Current (Power-Down)
SYMBOL
V
OH
V
OL
V
OL1
V
OL2
I
IH
I
IL
I
CC
I
CCQ
I
OL
= 4mA
3mA sink current
6mA sink current
V
CC
= 3.6V
V
IL
= 0V
C
L
= 15pF (output at default frequency)
Power-down mode
-1
10
10
CONDITIONS
I
OH
= -4mA, V
CC
= min
MIN
2.4
0
0
0
0.4
0.4
0.6
1
TYP
MAX
UNITS
V
V
V
μA
μA
mA
μA
2
Maxim Integrated
DS1086L
3.3V Spread-Spectrum EconOscillator
MASTER OSCILLATOR CHARACTERISTICS
(V
CC
= 2.7V to 3.6V, T
A
= -40°C to +85°C.)
PARAMETER
Master Oscillator Frequency
Default Master Oscillator Frequency
Master Oscillator Frequency
Tolerance
Voltage Frequency Variation
SYMBOL
f
OSC
f
0
Δ
f
0
f
0
Δ
f
V
f
0
Δ
f
T
f
0
(Note 2)
Factory-programmed default
V
CC
= 3.3V,
T
A
= +25°C
(Notes 3,17)
Over voltage range,
T
A
= +25°C (Note 4)
Over temperature
range, V
CC
= 3.3V
(Note 5)
Default frequency (f
0
)
DAC step size
Default frequency
DAC step size
Default frequency
66.6MHz
33.3MHz
-0.5
-0.5
-0.75
-0.75
-2.0
-2.0
-2.5
0.5
1
2
4
8
-0.6
5
5.12
500
2.56
RANGE
(5 LSBs of
RANGE register)
f
0
/8192
f
0
/4096
f
0
/2048
Hz
+0.3
%
kHz
MHz
decimal
MHz
%
CONDITIONS
MIN
33.3
48.65
+0.5
%
+0.5
+0.75
+0.75
+0.75
+0.75
+0.75
%
%
TYP
MAX
66.6
UNITS
MHz
MHz
Temperature Frequency Variation
Prescaler bits JS2, JS1, JS0 = 000
Dither Frequency Range (Note 6)
Δ
f
f
0
Prescaler bits JS2, JS1, JS0 = 001
Prescaler bits JS2, JS1, JS0 = 010
Prescaler bits JS2, JS1, JS0 = 100
Prescaler bits JS2, JS1, JS0 = 111
Integral Nonlinearity of Frequency
DAC Step Size
DAC Span
DAC Default
Offset Step Size
INL
Entire range (Note 7)
Δ
between two consecutive DAC values
(Note 8)
Frequency range for one offset setting
(Table 2)
Factory default register setting
Δ
between two consecutive offset values
(Table 2)
OS
Factory default OFFSET register setting
(5 LSBs) (Table 2)
Prescaler bits JS4, JS3 = 00
Dither Rate
Prescaler bits JS4, JS3 = 01
Prescaler bits JS4, JS3 = 10
Offset Default
hex
Maxim Integrated
3
DS1086L
3.3V Spread-Spectrum EconOscillator
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V to 3.6V, T
A
= -40°C to +85°C.)
PARAMETER
Frequency Stable After Prescaler
Change
Frequency Stable After DAC or
Offset Change
Power-Up Time
Enable of OUT After Exiting
Power-Down Mode
OUT High-Z After Entering
Power-Down Mode
Load Capacitance
Output Duty Cycle (OUT)
Rise and Fall Time (OE,
PDN)
t
DACstab
(Note 9)
0.1
0.1
SYMBOL
CONDITIONS
MIN
TYP
MAX
1
1
0.5
200
100
(Note 11)
Default frequency
45
15
50
55
1
UNITS
period
ms
ms
μs
μs
pF
%
μs
t
por
+ t
stab
(Note 10)
t
stab
t
pdn
C
L
(Note 18)
AC ELECTRICAL CHARACTERISTICS—2-WIRE INTERFACE
(V
CC
= 2.7V to 3.6V, T
A
= -40°C to +85°C.)
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP
and START Condition
Hold Time (Repeated) START
Condition
LOW Period of SCL
HIGH Period of SCL
Setup Time for a Repeated
START
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
SYMBOL
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
CONDITIONS
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
(Note 12)
(Note 12)
(Notes 12, 13)
(Note 12)
(Note 12)
(Note 12)
(Notes 12, 14, 15)
(Note 12)
(Note 16)
(Note 16)
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0
100
250
20 + 0.1C
B
20 + 0.1C
B
20 + 0.1C
B
20 + 0.1C
B
0.9
MIN
TYP
MAX
400
100
UNITS
kHz
μs
μs
μs
μs
μs
μs
ns
300
1000
300
1000
ns
ns
4
Maxim Integrated
DS1086L
3.3V Spread-Spectrum EconOscillator
AC ELECTRICAL CHARACTERISTICS—2-WIRE INTERFACE (continued)
(V
CC
= 2.7V to 3.6V, T
A
= -40°C to +85°C.)
PARAMETER
Setup Time for STOP
Capacitive Load for Each Bus
Line
EEPROM Write Cycle Time
Input Capacitance
SYMBOL
t
SU:STO
C
B
t
WR
C
I
5
Fast mode
Standard mode
(Note 16)
CONDITIONS
MIN
0.6
4.0
400
10
TYP
MAX
UNITS
μs
pF
ms
pF
NONVOLATILE MEMORY CHARACTERISTICS
(V
CC
= 2.7V to 3.6V)
PARAMETER
EEPROM Writes
SYMBOL
+70°C
CONDITIONS
MIN
10,000
TYP
MAX
UNITS
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
All voltages are referenced to ground.
DAC and OFFSET register settings must be configured to maintain the master oscillator frequency within this range.
Correct operation of the device is not guaranteed if these limits are exceeded.
This is the absolute accuracy of the master oscillator frequency at the default settings.
This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at
T
A
= +25°C.
This is the percentage frequency change from the +25°C frequency due to temperature at V
CC
= 3.3V. The maximum temper-
ature change varies with the master oscillator frequency setting. The minimum occurs at the default master oscillator frequen-
cy (f
default
). The maximum occurs at the extremes of the master oscillator frequency range (33.3MHz or 66.6MHz).
The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency.
The integral nonlinearity of the frequency is a measure of the deviation from a straight line drawn between the two end-
points (f
osc(MIN)
to f
osc(MAX)
) of the range. The error is in percentage of the span.
This is true when the prescaler = 1.
Frequency settles faster for small changes in value. During a change, the frequency transitions smoothly from the original
value to the new value.
This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally
introduced to allow the oscillator to stabilize. t
stab
is equivalent to approximately 512 master clock cycles and therefore
depends on the programmed clock frequency.
Output voltage swings can be impaired at high frequencies combined with high output loading.
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
> 250ns must then be met.
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line at least t
R MAX
+ t
SU:DAT
=
1000ns + 250ns = 1250ns before the SCL line is released.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
IH MIN
of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
need only be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
C
B
—total capacitance of one bus line, timing referenced to 0.9 x V
CC
and 0.1 x V
CC
.
Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr
+125°C bake, 168hr 85°C/85%RH moisture soak, and three solder reflow passes +240 +0/-5°C peak) followed by 1000hr
max V
CC
biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, 96hr 130°C/85%RH/3.6V HAST and 168hr
121°C/2 ATM Steam/Unbiased Autoclave.
t
stab
is the time required after exiting power-down to the beginning of output oscillations. In addition, a delay of t
DACstab
is required before the frequency will be within its specified tolerance.
Maxim Integrated
5
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