performance oscillators utilize a proven silicon MEMS
technology to provide excellent jitter and stability over
a wide range of supply voltages and temperatures. By
eliminating the need for quartz or SAW technology,
MEMS oscillators significantly enhance reliability and
accelerate product development, while meeting
stringent clock performance criteria for a variety of
communications, storage, and networking applications.
DSC1101 has a standby feature that allows it to
completely power-down when EN pin is pulled low;
whereas for DSC1121, only the outputs are disabled
when EN is low. Both oscillators are available in
industry standard packages, including the small
2.5 mm x 2.0 mm, and are “drop-in” replacements for
standard 4-pin CMOS quartz crystal oscillators.
Functional Block Diagram
Applications
• Storage Area Networks
- SATA, SAS, Fibre Channel
• Passive Optical Networks
- EPON, 10G-EPON,V GPON, 10G-PON
• Ethernet
- 1G, 10GBASE-T/KR/LR/SR, and FCoE
• HD/SD/SDI Video and Surveillance
• PCI Express
• Display Port
2017 Microchip Technology Inc.
DS20005613B-page 1
DSC1101/21
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Input Voltage, V
IN
..............................................................................................................................–0.3V to V
DD
+ 0.3V
Supply Voltage .......................................................................................................................................... –0.3V to +4.0V
ESD Protection On All Pins ........................................................................................... 4000V HBM, 1500V CDM (max.)
† Notice:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Note:
1000+ years of data retention on internal memory.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics
Parameters
Supply Voltage (Note
1)
Sym.
V
DD
Min.
2.25
—
Supply Current
I
DD
—
—
Frequency Stability
(Including frequency
variations due to initial
tolerance, temp. and
power supply voltage.)
Aging
Startup Time (Note
2)
Input Logic Levels
Input Logic High
Input Logic Low
Output Disable Time
(Note
3)
Output Enable Time
Enable Pull-up Resistor
(Note
4)
CMOS Output
Output Logic Levels
Output Logic High
Output Logic Low
Note 1:
2:
3:
4:
V
OH
V
OL
0.9
V
DD
—
—
—
—
0.1
V
DD
V
I = ±6 mA
—
Typ.
—
—
20
31
—
—
—
—
—
—
—
—
—
—
40
Max.
3.6
0.095
22
35
±10
±20
—
—
—
—
0.75
V
DD
—
—
—
—
—
±25
±50
±5
5
—
0.1
V
DD
5
5
20
—
V
ns
ms
ns
k
—
—
DSC1101
DSC1121
Pull-up Resistor Exist
ppm
ms
ppm
mA
Units
V
—
DSC1101, EN pin low, output
is disabled
DSC1121, EN pin low, output
is disabled
Output enabled, C
L
= 15 pF,
F
0
= 100 MHz
Ext Comm. & Ind. only
All temp ranges
All temp ranges
All temp ranges
1 year @ 25°C
T = 25°C
Conditions
f
f
t
SU
V
IH
V
IL
t
DS
t
EN
—
Pin 6 V
DD
should be filtered with 0.1 µF capacitor.
t
SU
is time to 100 ppm of output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures define the parameters.
Output is enabled if pad is floated or not connected.
DS20005613B-page 2
2017 Microchip Technology Inc.
DSC1101/21
TABLE 1-1:
DC CHARACTERISTICS (CONTINUED)
Electrical Characteristics
Parameters
Output Transition Time
Rise Time
Fall Time
Sym.
t
R
t
F
Min.
—
—
2.3
Frequency
f
0
3.3
Output Duty Cycle
Period Jitter
Integrated Phase Noise
SYM
J
PER
J
PH
45
—
—
—
—
Note 1:
2:
3:
4:
—
—
3
0.3
0.38
1.7
170
55
—
—
—
2
ps
RMS
%
ps
RMS
Typ.
1.1
1.3
—
Max.
2
2
170
MHz
ns
Units
Conditions
20% to 80%
C
L
= 15 pF
C
L
= 15 pF, –20°C to +70°C
and –40°C to +85°C
C
L
= 15 pF, –40°C to +105°C
and –55°C to +125°C
—
F
OUT
= 125 MHz
200 kHz to 20 MHz @ 125 MHz
100 kHz to 20 MHz @ 125 MHz
12 kHz to 20 MHz @ 125 MHz
Pin 6 V
DD
should be filtered with 0.1 µF capacitor.
t
SU
is time to 100 ppm of output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures define the parameters.
Output is enabled if pad is floated or not connected.
2017 Microchip Technology Inc.
DS20005613B-page 3
DSC1101/21
TEMPERATURE SPECIFICATIONS (Note
1)
Parameters
Temperature Ranges
T
A
Operating Temperature Range (T)
T
A
T
A
T
A
Junction Operating Temperature
Storage Temperature Range
Soldering Temperature Range
Note 1:
T
J
T
A
T
S
–20
–40
–40
–55
—
–40
—
—
—
—
—
—
—
—
+70
+85
+105
+125
+150
+150
+260
°C
°C
°C
°C
°C
°C
°C
Ordering Option E
Ordering Option I
Ordering Option L
Ordering Option M
—
—
40 sec. max
Sym.
Min.
Typ.
Max.
Units
Conditions
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable
junction temperature and the thermal resistance from junction to air (i.e., T
A
, T
J
,
JA
). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.
DS20005613B-page 4
2017 Microchip Technology Inc.
DSC1101/21
2.0
Note:
NOMINAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
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FPGA/CPLD
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