Data Sheet No. PD60026-R
IR2112(S) & (PbF)
HIGH AND LOW SIDE DRIVER
Features
•
Floating channel designed for bootstrap operation
•
Fully operational to +600V
•
Tolerant to negative transient voltage
•
•
•
•
•
•
•
•
dV/dt immune
Gate drive supply range from 10 to 20V
Undervoltage lockout for both channels
3.3V logic compatible
Separate logic supply range from 3.3V to 20V
Logic and power ground ±5V offset
CMOS Schmitt-triggered inputs with pull-down
Cycle by cycle edge-triggered shutdown logic
Matched propagation delay for both channels
Outputs in phase with inputs
Also available LEAD-FREE
Product Summary
V
OFFSET
I
O
+/-
V
OUT
t
on/off
(typ.)
Delay Matching
600V max.
200 mA / 420 mA
10 - 20V
125 & 105 ns
30 ns
Packages
Description
The IR2112(S) is a high voltage, high speed power
MOSFET and IGBT driver with independent high and
low side referenced output channels. Proprietary HVIC
16-Lead SOIC
(wide body)
14-Lead PDIP
and latch immune CMOS technologies enable rugge-
dized monolithic construction. Logic inputs are com-
patible with standard CMOS or LSTTL outputs, down
to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-
conduction. Propagation delays are matched to simplify use in high frequency applications. The floating
channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which
operates up to 600 volts.
Typical Connection
HO
V
DD
HIN
SD
LIN
V
SS
V
CC
V
DD
HIN
SD
LIN
V
SS
V
CC
COM
LO
V
B
V
S
up to 600V
TO
LOAD
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.
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1
IR2112(S) & (PbF)
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
DD
V
SS
V
IN
dV
s
/dt
P
D
R
THJA
T
J
T
S
T
L
Definition
High Side Floating Supply Voltage
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
Logic Supply Voltage
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
Allowable Offset Supply Voltage Transient (Figure 2)
Package Power Dissipation @ T
A
≤
+25° C
Thermal Resistance, Junction to Ambient
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
(14 Lead DIP)
(16 Lead SOIC)
(14 Lead DIP)
(16 Lead SOIC)
Min.
-0.3
V
B
- 25
V
S
- 0.3
-0.3
-0.3
-0.3
V
CC
- 25
V
SS
- 0.3
—
—
—
—
—
—
-55
—
Max.
625
V
B
+ 0.3
V
B
+ 0.3
25
V
CC
+ 0.3
V
SS
+ 25
V
CC
+ 0.3
V
DD
+ 0.3
50
1.6
1.25
75
100
150
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The VS and V SS offset ratings are tested with all supplies biased at 15V differential. Typical
ratings at other bias conditions are shown in Figures 36 and 37.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
DD
V
SS
V
IN
T
A
Definition
High Side Floating Supply Absolute Voltage
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
Logic Supply Voltage
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
Ambient Temperature
Min.
V
S
+ 10
Note 1
V
S
10
0
V
SS
+ 3
-5 (Note 2)
V
SS
-40
Max.
V
S
+ 20
600
V
B
20
V
CC
V
SS
+ 20
5
V
DD
125
Units
V
°C
Note 1:
Logic operational for V
S
of -5 to +600V. Logic state held for V
S
of -5V to -V
BS
. (Please refer to the Design Tip
DT97-3 for more details).
Note 2:
When V
DD
< 5V, the minimum V
SS
offset is limited to -V
DD
.
2
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IR2112(S) & (PbF)
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
, V
DD
) = 15V, C
L
= 1000 pF, T
A
= 25°C and V
SS
= COM unless otherwise specified. The dynamic
electrical characteristics are measured using the test circuit shown in Figure 3.
Symbol
t
on
t
off
t
sd
t
r
t
f
MT
Definition
Turn-On Propagation Delay
Turn-Off Propagation Delay
Shutdown Propagation Delay
Turn-On Rise Time
Turn-Off Fall Time
Delay Matching, HS & LS Turn-On/Off
Figure Min. Typ. Max. Units Test Conditions
7
8
9
10
11
—
—
—
—
—
—
—
125
105
105
80
40
—
180
160
160
130
65
30
V
S
= 0V
V
S
= 600V
V
S
= 600V
ns
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
, V
DD
) = 15V, T
A
= 25°C and V
SS
= COM unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters
are referenced to V
SS
and are applicable to all three logic input leads: HIN, LIN and SD. The V
O
and I
O
parameters are
referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
V
IH
V
IL
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
QDD
I
IN+
I
IN-
V
BSUV+
V
BSUV-
V
CCUV+
V
CCUV-
I
O+
I
O-
Definition
Logic “1” Input Voltage
Logic “0” Input Voltage
High Level Output Voltage, V
BIAS
- V
O
Low Level Output Voltage, V
O
Offset Supply Leakage Current
Quiescent V
BS
Supply Current
Quiescent V
CC
Supply Current
Quiescent V
DD
Supply Current
Logic “1” Input Bias Current
Logic “0” Input Bias Current
V
BS
Supply Undervoltage Positive Going
Threshold
V
BS
Supply Undervoltage Negative Going
Threshold
V
CC
Supply Undervoltage Positive Going
Threshold
V
CC
Supply Undervoltage Negative Going
Threshold
Output High Short Circuit Pulsed Current
Output Low Short Circuit Pulsed Current
Figure Min. Typ. Max. Units Test Conditions
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
9.5
—
—
—
—
—
—
—
—
—
7.4
7.0
7.6
7.2
200
420
—
—
—
—
—
25
80
2.0
20
—
8.5
8.1
8.6
8.2
250
500
—
6.0
100
100
50
60
180
5.0
40
1.0
9.6
9.2
V
9.6
9.2
—
—
mA
V
O
= 0V, V
IN
= V
DD
PW
≤
10
µs
V
O
= 15V, V
IN
= 0V
PW
≤
10
µs
µA
V
mV
I
O
= 0A
I
O
= 0A
V
B
= V
S
= 600V
V
IN
= 0V or V
DD
V
IN
= 0V or V
DD
V
IN
= 0V or V
DD
V
IN
= V
DD
V
IN
= 0V
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3
IR2112(S) & (PbF)
Functional Block Diagram
V
B
V
DD
R Q
S
HIN
HV
LEVEL
SHIFT
UV
DETECT
PULSE
FILTER
R
R
S
Q
HO
V
DD
/V
CC
LEVEL
SHIFT
PULSE
GEN
V
S
SD
UV
DETECT
V
CC
V
DD
/V
CC
LEVEL
SHIFT
LIN
S
R Q
V
SS
LO
DELAY
COM
Lead Definitions
Symbol
V
DD
HIN
SD
LIN
V
SS
V
B
HO
V
S
V
CC
LO
COM
Description
Logic supply
Logic input for high side gate driver output (HO), in phase
Logic input for shutdown
Logic input for low side gate driver output (LO), in phase
Logic ground
High side floating supply
High side gate drive output
High side floating supply return
Low side supply
Low side gate drive output
Low side return
Lead Assignments
14 Lead DIP
16 Lead SOIC (Wide Body)
IR2112
Part Number
4
IR2112S
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IR2112(S) & (PbF)
<50 V/ns
Figure 1. Input/Output Timing Diagram
Figure 2. Floating Supply Voltage Transient Test
Circuit
HIN
LIN
ton
50%
50%
tr
90%
toff
90%
tf
HO
LO
10%
10%
Figure 3. Switching Time Test Circuit
Figure 4. Switching Time Waveform Definition
HIN
LIN
50%
50%
50%
SD
tsd
LO
HO
10%
HO
LO
90%
MT
90%
MT
LO
Figure 5. Shutdown Waveform Definitions
HO
Figure 6. Delay Matching Waveform Definitions
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