PAL20R4-7PC datasheet, PDF - EEWORLD Datasheet

PAL20R4-7PC: DescriptionOT PLD, 25 ns, CDIP24; CategoryProgrammable logic devices Programmable logic; File Size2MB，45 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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PAL20R4-7PC Overview

OT PLD, 25 ns, CDIP24

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	AMD
Parts packaging code	DIP
package instruction	DIP, DIP24,.3
Contacts	24
Reach Compliance Code	unknow
Other features	POWER-UP RESET; 1 EXTERNAL CLOCK; REGISTER PRELOAD
Architecture	PAL-TYPE
maximum clock frequency	74 MHz
JESD-30 code	R-PDIP-T24
JESD-609 code	e0
length	30.734 mm
Dedicated input times	12
Number of I/O lines	4
Number of entries	16
Output times	8
Number of product terms	64
Number of terminals	24
Maximum operating temperature	75 °C
Minimum operating temperature
organize	12 DEDICATED INPUTS, 4 I/O
Output function	MIXED
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	OT PLD
propagation delay	10 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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