XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET
OCTOBER 2007
REV. 1.0.3
GENERAL DESCRIPTION
The XRT75R12D is a twelve channel fully integrated
Line Interface Unit (LIU) featuring EXAR’s R
3
Technology (Reconfigurable, Relayless Redundancy)
for E3/DS3/STS-1 applications. The LIU incorporates
12 independent Receivers, Transmitters and Jitter
Attenuators in a single 420 Lead TBGA package.
Each channel of the XRT75R12D can be
independently configured to operate in E3 (34.368
MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz).
Each transmitter can be turned off and tri-stated for
redundancy support or for conserving power.
The XRT75R12D’s differential receiver provides high
noise interference margin and is able to receive data
over 1000 feet of cable or with up to 12 dB of cable
attenuation.
The XRT75R12D incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT 75R12D
Bellcore GR-499 specifications. Also, the jitter
attenuators can be used for clock smoothing in
SONET STS-1 to DS-3 de-mapping.
The XRT75R12D provides a Parallel Microprocessor
Interface for programming and control.
The XRT75R12D supports analog, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
APPLICATIONS
•
E3/DS3 Access Equipment
•
DSLAMs
•
Digital Cross Connect Systems
•
CSU/DSU Equipment
•
Routers
•
Fiber Optic Terminals
CS
RD
WR
Addr[7:0]
D[7:0]
PCLK
RDY
INT
Pmode
RESET
XRT75R12D
XRT75R12D
µProcessor
Interface
CLKOUT_n
SFM_en
RLOL_n
E3Clk
DS3Clk
STS-Clk/12M
MUX
Peak Detector
Slicer
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
Jitter
Attenuator
HDB3/
B3ZS
Decoder
RTIP_n
RRing_n
AGC/
Equalizer
RxClk_n
RxPOS_n
RxNEG/LCV_n
Local
LoopBack
Remote
LoopBack
RLOS_n
TxClk_n
TxPOS_n
TxNEG_n
TTIP_n
TRing_n
MTIP_n
MRing_n
DMO_n
ICT
Line
Driver
Tx
Pulse
Shaping
Timing
Control
Jitter
Attenuator
MUX
HDB3/
B3ZS
Encoder
Device
Monitor
Tx
Control
TxON
Channel 0
Channel n...
Channel 11
ORDERING INFORMATION
P
ART
N
UMBER
XRT75R12DIB
P
ACKAGE
420 Lead TBGA
O
PERATING
T
EMPERATURE
R
ANGE
-40
°
C to +85
°
C
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
FEATURES
RECEIVER
•
Each channel supports Analog, Remote and Digital
Loop-backs
(Reconfigurable,
Relayless
•
R
3
Technology
Redundancy)
input jitter tolerance
•
Single 3.3 V ± 5% power supply
•
5 V Tolerant digital inputs
•
Available in 420 pin TBGA Thermally enhanced
Package
•
On chip Clock and Data Recovery circuit for high
•
Meets E3/DS3/STS-1 Jitter Tolerance Requirement
•
Detects and Clears LOS as per G.775
•
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
•
- 40°C to 85°C Industrial Temperature Range
TRANSMIT INTERFACE CHARACTERISTICS
•
Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal
to the line
•
On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
•
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
•
Integrated Pulse Shaping Circuit
•
Built-in B3ZS/HDB3 Encoder (which can be
disabled)
•
Provides low jitter output clock
TRANSMITTER
•
Accepts Transmit Clock with duty cycle of 30%-
70%
•
Technology
Redundancy)
R
3
•
Generates pulses that comply with the ITU-T G.703
(Reconfigurable,
Relayless
pulse template for E3 applications
•
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
•
Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499
-CORE
and ANSI T1.102_1993
•
Tri-state Transmit output capability for redundancy
applications
•
Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253-
CORE
•
Each Transmitter can be independently turned on
or off
•
Transmitter can be turned off in order to support
redundancy designs
RECEIVE INTERFACE CHARACTERISTICS
•
Transmitters provide Voltage Output Drive
JITTER ATTENUATOR
•
On chip advanced crystal-less Jitter Attenuator for
each channel
•
Integrated Adaptive Receive Equalization (optional)
for optimal Clock and Data Recovery
•
Jitter Attenuator can be selected in Receive,
Transmit path, or disabled
•
Declares and Clears the LOS defect per ITU-T
G.775 requirements for E3 and DS3 applications
•
Meets ETSI TBR 24 Jitter Transfer Requirements
•
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
•
Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 for E3 Applications
•
Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE for DS3 Applications
•
16 or 32 bits selectable FIFO size
CONTROL AND DIAGNOSTICS
•
Declares Loss of Lock (LOL) Alarm
•
Built-in B3ZS/HDB3 Decoder (which can be
disabled)
•
Parallel Microprocessor Interface for control and
configuration
•
Recovered Data can be muted while the LOS
Condition is declared
•
Supports
monitoring
optional
internal
Transmit
driver
•
Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment
2
XRT75R12D
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TABLE OF CONTENTS
GENERAL DESCRIPTION.............................................................................................................. 1
A
PPLICATIONS
............................................................................................................................................................... 1
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT 75R12D.................................................................................................................................. 1
ORDERING INFORMATION .................................................................................................................... 1
F
EATURES
..................................................................................................................................................................... 2
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
....................................................................................................................... 2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
......................................................................................................................... 2
PIN DESCRIPTIONS (BY FUNCTION) ........................................................................................... 3
S
YSTEM
-S
IDE
T
RANSMIT
I
NPUT AND
T
RANSMIT
C
ONTROL
P
INS
....................................................................................... 3
S
YSTEM
-S
IDE
R
ECEIVE
O
UTPUT AND
R
ECEIVE
C
ONTROL
P
INS
....................................................................................... 6
R
ECEIVE
L
INE
S
IDE
P
INS
............................................................................................................................................... 8
C
LOCK
I
NTERFACE
......................................................................................................................................................... 9
G
ENERAL
C
ONTROL
P
INS
............................................................................................................................................ 10
P
OWER
S
UPPLY
P
INS
.................................................................................................................................................. 12
G
ROUND
P
INS
............................................................................................................................................................. 13
T
ABLE
1: L
IST BY
P
IN
N
UMBER
............................................................................................................................................................. 14
FUNCTIONAL DESCRIPTION ...................................................................................................... 18
1.0 R3 TECHNOLOGY (RECONFIGURABLE, RELAYLESS REDUNDANCY) ....................................... 18
1.1 NETWORK ARCHITECTURE ......................................................................................................................... 18
F
IGURE
2. N
ETWORK
R
EDUNDANCY
A
RCHITECTURE
.............................................................................................................................. 18
2.0 CLOCK SYNTHESIZER ....................................................................................................................... 19
F
IGURE
3. S
IMPLIFIED
B
LOCK
D
IAGRAM OF THE
I
NPUT
C
LOCK
C
IRCUITRY
D
RIVING THE
M
ICROPROCESSOR
............................................ 19
T
ABLE
2: R
EFERENCE
C
LOCK
P
ERFORMANCE
S
PECIFICATIONS
.............................................................................................................. 19
2.1 CLOCK DISTRIBUTION ................................................................................................................................. 20
F
IGURE
4. C
LOCK
D
ISTRIBUTION
C
ONGIFURED IN
E3 M
ODE
W
ITHOUT
U
SING
SFM ................................................................................ 20
3.0 THE RECEIVER SECTION .................................................................................................................. 21
F
IGURE
5. R
ECEIVE
P
ATH
B
LOCK
D
IAGRAM
.......................................................................................................................................... 21
3.1 RECEIVE LINE INTERFACE .......................................................................................................................... 21
F
IGURE
6. R
ECEIVE
L
INE
I
NTERFACE
C
ONNECTION
................................................................................................................................. 21
3.2 ADAPTIVE GAIN CONTROL (AGC) .............................................................................................................. 21
3.3 RECEIVE EQUALIZER ................................................................................................................................... 22
F
IGURE
7. ACG/E
QUALIZER
B
LOCK
D
IAGRAM
....................................................................................................................................... 22
3.3.1 RECOMMENDATIONS FOR EQUALIZER SETTINGS .............................................................................................. 22
3.4 CLOCK AND DATA RECOVERY ................................................................................................................... 22
3.4.1 DATA/CLOCK RECOVERY MODE ............................................................................................................................ 22
3.4.2 TRAINING MODE........................................................................................................................................................ 22
3.5 LOS (LOSS OF SIGNAL) DETECTOR ........................................................................................................... 23
3.5.1 DS3/STS-1 LOS CONDITION ..................................................................................................................................... 23
T
ABLE
3: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION AND
C
LEARANCE
T
HRESHOLDS FOR A GIVEN SETTING OF
REQEN (DS3
AND
STS-1 A
P
-
PLICATIONS
).......................................................................................................................................................................... 23
3.5.2 DISABLING ALOS/DLOS DETECTION ..................................................................................................................... 23
3.5.3 E3 LOS CONDITION:.................................................................................................................................................. 23
F
IGURE
8. L
OSS
O
F
S
IGNAL
D
EFINITION FOR
E3
AS PER
ITU-T G.775 .................................................................................................. 23
F
IGURE
9. L
OSS OF
S
IGNAL
D
EFINITION FOR
E3
AS PER
ITU-T G.775................................................................................................... 24
3.5.4 INTERFERENCE TOLERANCE.................................................................................................................................. 24
F
IGURE
10. I
NTERFERENCE
M
ARGIN
T
EST
S
ET UP FOR
DS3/STS-1 ...................................................................................................... 24
F
IGURE
11. I
NTERFERENCE
M
ARGIN
T
EST
S
ET UP FOR
E3. ................................................................................................................... 24
T
ABLE
4: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
................................................................................................................................. 25
3.5.5 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 26
F
IGURE
12. R
ECEIVER
D
ATA OUTPUT AND CODE VIOLATION TIMING
........................................................................................................ 26
3.6 B3ZS/HDB3 DECODER .................................................................................................................................. 26
4.0 JITTER ................................................................................................................................................. 27
4.1 JITTER TOLERANCE ..................................................................................................................................... 27
F
IGURE
13. J
ITTER
T
OLERANCE
M
EASUREMENTS
.................................................................................................................................. 27
4.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS ................................................................................................ 27
F
IGURE
14. I
NPUT
J
ITTER
T
OLERANCE
F
OR
DS3/STS-1 ...................................................................................................................... 28
4.1.2 E3 JITTER TOLERANCE REQUIREMENTS.............................................................................................................. 28
F
IGURE
15. I
NPUT
J
ITTER
T
OLERANCE FOR
E3 .................................................................................................................................... 28
T
ABLE
5: J
ITTER
A
MPLITUDE VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
) ........................................................................... 29
4.2 JITTER TRANSFER ........................................................................................................................................ 29
I
XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
T
ABLE
6: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
..................................................................................................................... 29
4.3 JITTER ATTENUATOR ................................................................................................................................... 29
T
ABLE
7: J
ITTER
T
RANSFER
P
ASS
M
ASKS
............................................................................................................................................. 30
F
IGURE
16. J
ITTER
T
RANSFER
R
EQUIREMENTS AND
J
ITTER
A
TTENUATOR
P
ERFORMANCE
...................................................................... 30
4.3.1 JITTER GENERATION................................................................................................................................................ 30
5.0 DIAGNOSTIC FEATURES ...................................................................................................................31
5.1 PRBS GENERATOR AND DETECTOR ......................................................................................................... 31
F
IGURE
17. PRBS MODE ................................................................................................................................................................... 31
5.2 LOOPBACKS .................................................................................................................................................. 32
5.2.1 ANALOG LOOPBACK ................................................................................................................................................ 32
F
IGURE
18. A
NALOG
L
OOPBACK
........................................................................................................................................................... 32
5.2.2 DIGITAL LOOPBACK ................................................................................................................................................. 33
F
IGURE
19. D
IGITAL
L
OOPBACK
............................................................................................................................................................ 33
5.2.3 REMOTE LOOPBACK ................................................................................................................................................ 33
F
IGURE
20. R
EMOTE
L
OOPBACK
........................................................................................................................................................... 33
5.3 TRANSMIT ALL ONES (TAOS) ...................................................................................................................... 34
F
IGURE
21. T
RANSMIT
A
LL
O
NES
(TAOS) ............................................................................................................................................ 34
6.0 THE TRANSMITTER SECTION ...........................................................................................................35
F
IGURE
22.
F
IGURE
23.
F
IGURE
24.
F
IGURE
25.
T
RANSMIT
P
ATH
B
LOCK
D
IAGRAM
....................................................................................................................................... 35
T
YPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE
XRT75R12D (
DUAL
-
RAIL DATA
)............................................ 35
T
RANSMITTER
T
ERMINAL
I
NPUT
T
IMING
............................................................................................................................... 36
S
INGLE
-R
AIL OR
NRZ D
ATA
F
ORMAT
(E
NCODER AND
D
ECODER ARE
E
NABLED
) .................................................................. 36
6.1 TRANSMIT CLOCK ........................................................................................................................................ 37
6.2 B3ZS/HDB3 ENCODER .................................................................................................................................. 37
6.2.1 B3ZS ENCODING ....................................................................................................................................................... 37
F
IGURE
27. B3ZS E
NCODING
F
ORMAT
................................................................................................................................................. 37
6.2.2 HDB3 ENCODING ....................................................................................................................................................... 37
F
IGURE
26. D
UAL
-R
AIL
D
ATA
F
ORMAT
(
ENCODER AND DECODER ARE DISABLED
).................................................................................... 37
F
IGURE
28. HDB3 E
NCODING
F
ORMAT
................................................................................................................................................. 38
6.3 TRANSMIT PULSE SHAPER ......................................................................................................................... 38
F
IGURE
29. T
RANSMIT
P
ULSE
S
HAPE
T
EST
C
IRCUIT
.............................................................................................................................. 38
6.3.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT .................................................................................. 38
6.4 E3 LINE SIDE PARAMETERS ........................................................................................................................ 39
F
IGURE
30. P
ULSE
M
ASK FOR
E3 (34.368
MBITS
/
S
)
INTERFACE AS PER ITU
-
T
G.703 ............................................................................. 39
T
ABLE
8: E3 T
RANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS
.............................................................. 39
F
IGURE
31. B
ELLCORE
GR-253 CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE FOR
SONET STS-1 A
PPLICATIONS
................................. 40
T
ABLE
9: STS-1 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................................................... 40
T
ABLE
10: STS-1 T
RANSMITTER
L
INE
S
IDE
O
UTPUT AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-253)................................... 41
F
IGURE
32. T
RANSMIT
O
UPUT
P
ULSE
T
EMPLATE FOR
DS3
AS PER
B
ELLCORE
GR-499 ......................................................................... 42
T
ABLE
11: DS3 P
ULSE
M
ASK
E
QUATIONS
............................................................................................................................................. 42
T
ABLE
12: DS3 T
RANSMITTER
L
INE
S
IDE
O
UTPUT AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-499) ...................................... 43
6.5 TRANSMIT DRIVE MONITOR ........................................................................................................................ 44
F
IGURE
33. T
RANSMIT
D
RIVER
M
ONITOR SET
-
UP
................................................................................................................................... 44
6.6 TRANSMITTER SECTION ON/OFF ............................................................................................................... 44
7.0 MICROPROCESSOR INTERFACE BLOCK ........................................................................................45
T
ABLE
13: S
ELECTING THE
M
ICROPROCESSOR
I
NTERFACE
M
ODE
.......................................................................................................... 45
F
IGURE
34. S
IMPLIFIED
B
LOCK
D
IAGRAM OF THE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
........................................................................ 45
7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 46
T
ABLE
14: XRT75R12D M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
......................................................................................................... 46
7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION .......................................................................... 47
F
IGURE
35. A
SYNCHRONOUS
µP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD AND
W
RITE
O
PERATIONS
.................................. 47
T
ABLE
15: A
SYNCHRONOUS
T
IMING
S
PECIFICATIONS
............................................................................................................................. 48
F
IGURE
36. S
YNCHRONOUS
µP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD AND
W
RITE
O
PERATIONS
.................................... 48
T
ABLE
16: S
YNCHRONOUS
T
IMING
S
PECIFICATIONS
............................................................................................................................... 49
7.3 REGISTER MAP ............................................................................................................................................. 50
T
ABLE
17: C
OMMAND
R
EGISTER
A
DDRESS
M
AP
,
WITHIN THE
XRT75R12D ........................................................................................... 50
THE GLOBAL/CHIP-LEVEL REGISTERS ................................................................................................................ 59
T
ABLE
18: L
IST AND
A
DDRESS
L
OCATIONS OF
G
LOBAL
R
EGISTERS
........................................................................................................ 59
REGISTER DESCRIPTION - GLOBAL REGISTERS ............................................................................................... 59
T
ABLE
19:
T
ABLE
20:
T
ABLE
21:
T
ABLE
22:
T
ABLE
23:
APS/R
EDUNDANCY
T
RANSMIT
C
ONTROL
R
EGISTER
- CR0 (A
DDRESS
L
OCATION
= 0
X
00) ..................................................... 59
APS/R
EDUNDANCY
R
ECIEVE
C
ONTROL
R
EGISTER
- CR8 (A
DDRESS
L
OCATION
= 0
X
08) ....................................................... 60
APS/R
EDUNDANCY
T
RANSMIT
C
ONTROL
R
EGISTER
- CR128 (A
DDRESS
L
OCATION
= 0
X
80) ................................................. 60
APS/R
EDUNDANCY
R
ECIEVE
C
ONTROL
R
EGISTER
- CR136 (A
DDRESS
L
OCATION
= 0
X
88) ................................................... 61
C
HANNEL
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- CR96 (A
DDRESS
L
OCATION
= 0
X
60) ......................................................... 62
II
XRT75R12D
REV. 1.0.3
T
ABLE
24:
T
ABLE
25:
T
ABLE
26:
T
ABLE
27:
T
ABLE
28:
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
C
HANNEL
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- CR224 (A
DDRESS
L
OCATION
= 0
X
E0)....................................................... 63
C
HANNEL
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- CR97 (A
DDRESS
L
OCATION
= 0
X
61) ......................................................... 64
C
HANNEL
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- CR225 (A
DDRESS
L
OCATION
= 0
X
E1)....................................................... 65
D
EVICE
/P
ART
N
UMBER
R
EGISTER
- CR110 (A
DDRESS
L
OCATION
= 0
X
6E) ........................................................................... 65
C
HIP
R
EVISION
N
UMBER
R
EGISTER
- CR111 (A
DDRESS
L
OCATION
= 0
X
6F) ......................................................................... 66
THE PER-CHANNEL REGISTERS........................................................................................................................... 67
REGISTER DESCRIPTION - PER CHANNEL REGISTERS .................................................................................... 67
T
ABLE
29:
T
ABLE
30:
T
ABLE
31:
T
ABLE
32:
T
ABLE
33:
T
ABLE
34:
T
ABLE
35:
T
ABLE
36:
T
ABLE
37:
T
ABLE
38:
T
ABLE
39:
T
ABLE
40:
T
ABLE
41:
T
ABLE
42:
XRT75R12D R
EGISTER
MAP
SHOWING
I
NTERRUPT
E
NABLE
R
EGISTERS
(IER_
N
) (
N
= [0:11]).............................................. 67
S
OURCE
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- C
HANNEL N
A
DDRESS
L
OCATION
= 0
XM
1 .................................................... 68
XRT75R12D R
EGISTER
MAP
SHOWING
I
NTERRUPT
S
TATUS
R
EGISTERS
(ISR_
N
) (
N
= [0:11]).............................................. 70
XRT75R12D R
EGISTER
MAP
SHOWING
A
LARM
S
TATUS
R
EGISTERS
(AS_
N
) (
N
= [0:11]) ..................................................... 72
XRT75R12D R
EGISTER
MAP
SHOWING
T
RANSMIT
C
ONTROL
R
EGISTERS
(TC_
N
) (
N
= [0:11]) ........................................... 76
XRT75R12D R
EGISTER
MAP
SHOWING
R
ECEIVE
C
ONTROL
R
EGISTERS
(RC_
N
) (
N
= [0:11]) ............................................... 78
XRT75R12D R
EGISTER
MAP
SHOWING
C
HANNEL
C
ONTROL
R
EGISTERS
(CC_
N
) (
N
= [0:11]) .............................................. 80
XRT75R12D R
EGISTER
MAP
SHOWING
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTERS
(JA_
N
) (
N
= [0:11]) ............................. 83
XRT75R12D R
EGISTER
MAP
SHOWING
E
RROR
C
OUNTER
MSB
YTE
R
EGISTERS
(EM_
N
) (
N
= [0:11]).................................. 84
E
RROR
C
OUNTER
MSB
YTE
R
EGISTER
- C
HANNEL N
A
DDRESS
L
OCATION
= 0
XM
A (
M
= 0-5 & 8-D) ....................................... 84
XRT75R12D R
EGISTER
MAP
SHOWING
E
RROR
C
OUNTER
LSB
YTE
R
EGISTERS
(EL_
N
) (
N
= [0:11])..................................... 84
E
RROR
C
OUNTER
LSB
YTE
R
EGISTER
- C
HANNEL N
A
DDRESS
L
OCATION
= 0
XM
B (
M
= 0-5 & 8-D) ........................................ 85
XRT75R12D R
EGISTER
MAP
SHOWING
E
RROR
C
OUNTER
H
OLDING
R
EGISTERS
(EH_
N
) (
N
= [0:11])................................... 85
E
RROR
C
OUNTER
H
OLDING
R
EGISTER
- C
HANNEL N
A
DDRESS
L
OCATION
= 0
XM
C (
M
= 0-5 & 8-D) ....................................... 86
8.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ............................................................... 87
8.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS ........................... 87
F
IGURE
37. A S
IMPLE
I
LLUSTRATION OF A
DS3
SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE
SONET N
ETWORK
............... 88
8.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................. 89
8.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................. 89
F
IGURE
38. A S
IMPLE
I
LLUSTRATION OF THE
SONET STS-1 F
RAME
..................................................................................................... 90
F
IGURE
39. A S
IMPLE
I
LLUSTRATION OF THE
STS-1 F
RAME
S
TRUCTURE WITH THE
TOH
AND THE
E
NVELOPE
C
APACITY
B
YTES
D
ESIGNATED
91
F
IGURE
40. T
HE
B
YTE
-F
ORMAT OF THE
TOH
WITHIN AN
STS-1 F
RAME
................................................................................................. 92
F
IGURE
41. T
HE
B
YTE
-F
ORMAT OF THE
TOH
WITHIN AN
STS-1 F
RAME
................................................................................................. 93
F
IGURE
42. I
LLUSTRATION OF THE
B
YTE
S
TRUCTURE OF THE
STS-1 SPE ............................................................................................. 94
F
IGURE
43. A
N
I
LLUSTRATION OF
T
ELCORDIA
GR-253-CORE'
S
R
ECOMMENDATION ON HOW MAP
DS3
DATA INTO AN
STS-1 SPE ......... 95
F
IGURE
44. A S
IMPLIFIED
"B
IT
-O
RIENTED
" V
ERSION OF
T
ELCORDIA
GR-253-CORE'
S
R
ECOMMENDATION ON HOW TO MAP
DS3
DATA INTO AN
STS-1 SPE.......................................................................................................................................................................... 95
8.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS ......................................... 96
F
IGURE
45. A S
IMPLE
I
LLUSTRATION OF A
DS3 D
ATA
-S
TREAM BEING
M
APPED INTO AN
STS-1 SPE,
VIA A
PTE .................................... 97
F
IGURE
46. A
N
I
LLUSTRATION OF THE
STS-1 SPE
TRAFFIC THAT WILL BE GENERATED BY THE
"S
OURCE
" PTE,
WHEN MAPPING IN A
DS3
SIGNAL
THAT HAS A BIT RATE OF
44.736M
BPS
+ 1
PPM
,
INTO AN
STS-1
SIGNAL
.................................................................................. 99
F
IGURE
47. A
N
I
LLUSTRATION OF THE
STS-1 SPE
TRAFFIC THAT WILL BE GENERATED BY THE
S
OURCE
PTE,
WHEN MAPPING A
DS3
SIGNAL
THAT HAS A BIT RATE OF
44.736M
BPS
- 1
PPM
,
INTO AN
STS-1
SIGNAL
................................................................................. 100
8.3
JITTER/WANDER DUE TO POINTER ADJUSTMENTS ............................................................................ 101
8.3.1 THE CONCEPT OF AN STS-1 SPE POINTER......................................................................................................... 101
F
IGURE
48. A
N
I
LLUSTRATION OF AN
STS-1 SPE
STRADDLING ACROSS TWO CONSECUTIVE
STS-1
FRAMES
......................................... 101
F
IGURE
49. T
HE
B
IT
-
FORMAT OF THE
16-B
IT
W
ORD
(
CONSISTING OF THE
H1
AND
H2
BYTES
)
WITH THE
10
BITS
,
REFLECTING THE LOCATION OF
THE
J1
BYTE
,
DESIGNATED
.................................................................................................................................................. 102
F
IGURE
50. T
HE
R
ELATIONSHIP BETWEEN THE
C
ONTENTS OF THE
"P
OINTER
B
ITS
" (
E
.
G
.,
THE
10-
BIT EXPRESSION WITHIN THE
H1
AND
H2
BYTES
)
AND THE
L
OCATION OF THE
J1 B
YTE WITHIN THE
E
NVELOPE
C
APACITY OF AN
STS-1 F
RAME
................................................ 102
8.3.2 POINTER ADJUSTMENTS WITHIN THE SONET NETWORK ................................................................................ 103
8.3.3 CAUSES OF POINTER ADJUSTMENTS ................................................................................................................. 103
F
IGURE
51. A
N
I
LLUSTRATION OF AN
STS-1
SIGNAL BEING PROCESSED VIA A
S
LIP
B
UFFER
.................................................................. 104
F
IGURE
52. A
N
I
LLUSTRATION OF THE
B
IT
F
ORMAT WITHIN THE
16-
BIT WORD
(
CONSISTING OF THE
H1
AND
H2
BYTES
)
WITH THE
"I"
BITS DES
-
IGNATED
............................................................................................................................................................................. 105
F
IGURE
53. A
N
I
LLUSTRATION OF THE
B
IT
-F
ORMAT WITHIN THE
16-
BIT WORD
(
CONSISTING OF THE
H1
AND
H2
BYTES
)
WITH THE
"D"
BITS DES
-
IGNATED
............................................................................................................................................................................. 106
8.3.4 WHY ARE WE TALKING ABOUT POINTER ADJUSTMENTS? ............................................................................. 107
8.4 CLOCK GAPPING JITTER ........................................................................................................................... 107
F
IGURE
54. I
LLUSTRATION OF THE
T
YPICAL
A
PPLICATIONS FOR THE
LIU
IN A
SONET D
E
-S
YNC
A
PPLICATION
...................................... 107
8.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE)
FOR DS3 APPLICATIONS .......................................................................................................................... 108
T
ABLE
43: S
UMMARY OF
"C
ATEGORY
I I
NTRINSIC
J
ITTER
R
EQUIREMENT PER
T
ELCORDIA
GR-253-CORE,
FOR
DS3
APPLICATIONS
...... 108
8.5.1 DS3 DE-MAPPING JITTER....................................................................................................................................... 109
8.5.2 SINGLE POINTER ADJUSTMENT ........................................................................................................................... 109
F
IGURE
55. I
LLUSTRATION OF
S
INGLE
P
OINTER
A
DJUSTMENT
S
CENARIO
............................................................................................. 109
8.5.3 POINTER BURST...................................................................................................................................................... 110
III
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