DS26524
Quad T1/E1/J1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26524 is a single-chip 4-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each channel is independently
configurable, supporting both long-haul and short-haul
lines.
FEATURES
Four Complete T1, E1, or J1 Long-Haul/Short-
Haul Transceivers (LIU plus Framer)
Independent T1, E1, or J1 Selections for Each
Transceiver
Internal Software-Selectable Transmit- and
Receive-Side Termination for 100Ω T1 Twisted
Pair, 110Ω J1 Twisted Pair, 120Ω E1 Twisted
Pair, and 75Ω E1 Coaxial Applications
Crystal-Less Jitter Attenuator can be Selected
for Transmit or Receive Path; Jitter Attenuator
Meets ETS CTR 12/13, ITU-T G.736, G.742,
G.823, and AT&T Pub 62411
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted for
T1 or E1 Usage in the Host Mode
Receive-Signal Level Indication from -2.5dB to
-36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments
Transmit Open- and Short-Circuit Detection
LIU LOS in Accordance with G.775, ETS 300
233, and T1.231
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
TYPICAL OPERATING CIRCUIT
DS26524
T1/E1/J1
NETWORK
T1/J1/E1
Transceiver
x4
BACKPLANE
Transmit Synchronizer
Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port
Alarm Detection and Insertion
T1 Framing Formats of D4, SLC-96, and ESF
TDM
ORDERING INFORMATION
PART
DS26524G
DS26524G+
DS26524GN
DS26524GN+
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
256 TE-CSBGA
256 TE-CSBGA
256 TE-CSBGA
256 TE-CSBGA
J1 Support
E1 G.704 and CRC-4 Multiframe
T1-to-E1 Conversion
Features Continued in Section
2.
+ Denotes lead-free/RoHS compliant device.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 112907
DS26524 Quad T1/E1/J1 Transceiver
TABLE OF CONTENTS
1.
1.1
DETAILED DESCRIPTION.................................................................................................9
M
AJOR
O
PERATING
M
ODES
.............................................................................................................9
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
FEATURE HIGHLIGHTS ..................................................................................................10
G
ENERAL
......................................................................................................................................10
L
INE
I
NTERFACE
............................................................................................................................10
C
LOCK
S
YNTHESIZER
....................................................................................................................10
J
ITTER
A
TTENUATOR
.....................................................................................................................10
F
RAMER
/F
ORMATTER
....................................................................................................................10
S
YSTEM
I
NTERFACE
......................................................................................................................11
HDLC C
ONTROLLERS
...................................................................................................................12
T
EST AND
D
IAGNOSTICS
................................................................................................................12
C
ONTROL
P
ORT
............................................................................................................................12
3.
4.
5.
6.
7.
7.1
APPLICATIONS ...............................................................................................................13
SPECIFICATIONS COMPLIANCE ...................................................................................14
ACRONYMS AND GLOSSARY .......................................................................................16
BLOCK DIAGRAMS.........................................................................................................17
PIN DESCRIPTIONS ........................................................................................................19
P
IN
F
UNCTIONAL
D
ESCRIPTION
......................................................................................................19
8.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
FUNCTIONAL DESCRIPTION .........................................................................................26
P
ROCESSOR
I
NTERFACE
................................................................................................................26
C
LOCK
S
TRUCTURE
.......................................................................................................................26
Backplane Clock Generation ............................................................................................................... 26
8.2.1
R
ESETS AND
P
OWER
-D
OWN
M
ODES
..............................................................................................28
I
NITIALIZATION AND
C
ONFIGURATION
..............................................................................................29
Example Device Initialization Sequence .............................................................................................. 29
8.4.1
G
LOBAL
R
ESOURCES
....................................................................................................................29
P
ER
-P
ORT
R
ESOURCES
................................................................................................................29
D
EVICE
I
NTERRUPTS
.....................................................................................................................29
S
YSTEM
B
ACKPLANE
I
NTERFACE
...................................................................................................31
Elastic Stores ....................................................................................................................................... 31
IBO Multiplexer..................................................................................................................................... 34
H.100 (CT Bus) Compatibility .............................................................................................................. 40
Receive and Transmit Channel Blocking Registers............................................................................. 41
Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 41
Receive Fractional Support (Gapped Clock Mode) ............................................................................. 41
T1 Framing........................................................................................................................................... 42
E1 Framing........................................................................................................................................... 45
T1 Transmit Synchronizer .................................................................................................................... 47
Signaling .............................................................................................................................................. 48
T1 Data Link......................................................................................................................................... 52
E1 Data Link......................................................................................................................................... 54
Maintenance and Alarms ..................................................................................................................... 55
E1 Automatic Alarm Generation .......................................................................................................... 58
Error-Count Registers .......................................................................................................................... 59
DS0 Monitoring Function...................................................................................................................... 61
Transmit Per-Channel Idle Code Insertion........................................................................................... 62
2 of 273
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.9
F
RAMERS
......................................................................................................................................42
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
8.9.9
8.9.10
8.9.11
DS26524 Quad T1/E1/J1 Transceiver
8.9.12
8.9.13
8.9.14
8.9.15
8.9.16
8.9.17
Receive Per-Channel Idle Code Insertion............................................................................................ 62
Per-Channel Loopback ........................................................................................................................ 62
E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) ................................................................... 62
T1 Programmable In-Band Loop Code Generator............................................................................... 63
T1 Programmable In-Band Loop Code Detection................................................................................ 64
Framer Payload Loopbacks ................................................................................................................. 65
8.10
8.10.1
8.10.2
HDLC C
ONTROLLERS
................................................................................................................66
Receive HDLC Controller..................................................................................................................... 66
Transmit HDLC Controller.................................................................................................................... 69
8.11
8.11.1
8.11.2
8.11.3
8.11.4
8.11.5
L
INE
I
NTERFACE
U
NITS
(LIU
S
)....................................................................................................71
LIU Operation....................................................................................................................................... 74
Transmitter ........................................................................................................................................... 75
Receiver ............................................................................................................................................... 78
Jitter Attenuator.................................................................................................................................... 81
LIU Loopbacks ..................................................................................................................................... 82
8.12
8.12.1
8.12.2
B
IT
-E
RROR
-R
ATE
T
EST
(BERT) F
UNCTION
................................................................................84
BERT Repetitive Pattern Set ............................................................................................................... 85
BERT Error Counter............................................................................................................................. 85
9.
9.1
DEVICE REGISTERS .......................................................................................................86
R
EGISTER
L
ISTINGS
......................................................................................................................86
Global Register List.............................................................................................................................. 88
Framer Register List............................................................................................................................. 89
LIU and BERT Register List................................................................................................................. 96
Global Register Bit Map ....................................................................................................................... 97
Framer Register Bit Map ...................................................................................................................... 98
LIU Register Bit Map .......................................................................................................................... 106
BERT Register Bit Map ...................................................................................................................... 106
9.1.1
9.1.2
9.1.3
9.2
R
EGISTER
B
IT
M
APS
......................................................................................................................97
9.2.1
9.2.2
9.2.3
9.2.4
9.3
9.4
9.5
9.6
G
LOBAL
R
EGISTER
D
EFINITIONS
..................................................................................................107
F
RAMER
R
EGISTER
D
EFINITIONS
.................................................................................................122
Receive Register Definitions.............................................................................................................. 122
Transmit Register Definitions............................................................................................................. 181
9.4.1
9.4.2
LIU R
EGISTER
D
EFINITIONS
.........................................................................................................216
BERT R
EGISTER
D
EFINITIONS
.....................................................................................................225
10.
FUNCTIONAL TIMING ...................................................................................................233
T1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
..........................................................................233
T1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
....................................................................238
E1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
..........................................................................243
E1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
....................................................................245
T
HERMAL
C
HARACTERISTICS
....................................................................................................249
L
INE
I
NTERFACE
C
HARACTERISTICS
..........................................................................................249
M
ICROPROCESSOR
B
US
AC C
HARACTERISTICS
........................................................................250
JTAG I
NTERFACE
T
IMING
.........................................................................................................259
S
YSTEM
C
LOCK
AC C
HARACTERISTICS
....................................................................................260
TAP C
ONTROLLER
S
TATE
M
ACHINE
.........................................................................................262
Test-Logic-Reset................................................................................................................................ 262
Run-Test-Idle ..................................................................................................................................... 262
Select-DR-Scan ................................................................................................................................. 262
Capture-DR ........................................................................................................................................ 262
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10.1
10.2
10.3
10.4
11.
OPERATING PARAMETERS.........................................................................................248
11.1
11.2
12.
AC TIMING CHARACTERISTICS ..................................................................................250
12.1
12.2
12.3
13.
JTAG BOUNDARY SCAN AND TEST ACCESS PORT ................................................261
13.1.1
13.1.2
13.1.3
13.1.4
13.1
DS26524 Quad T1/E1/J1 Transceiver
13.1.5
13.1.6
13.1.7
13.1.8
13.1.9
13.1.10
13.1.11
13.1.12
13.1.13
13.1.14
13.1.15
13.1.16
Shift-DR.............................................................................................................................................. 262
Exit1-DR............................................................................................................................................. 262
Pause-DR........................................................................................................................................... 262
Exit2-DR............................................................................................................................................. 262
Update-DR ......................................................................................................................................... 262
Select-IR-Scan ............................................................................................................................... 262
Capture-IR ...................................................................................................................................... 263
Shift-IR............................................................................................................................................ 263
Exit1-IR........................................................................................................................................... 263
Pause-IR......................................................................................................................................... 263
Exit2-IR........................................................................................................................................... 263
Update-IR ....................................................................................................................................... 263
SAMPLE:PRELOAD .......................................................................................................................... 265
BYPASS ............................................................................................................................................. 265
EXTEST ............................................................................................................................................. 265
CLAMP............................................................................................................................................... 265
HIGHZ ................................................................................................................................................ 265
IDCODE ............................................................................................................................................. 265
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
I
NSTRUCTION
R
EGISTER
...........................................................................................................265
13.3
13.4
13.4.1
13.4.2
13.4.3
JTAG ID C
ODES
......................................................................................................................266
T
EST
R
EGISTERS
.....................................................................................................................266
Boundary Scan Register .................................................................................................................... 266
Bypass Register ................................................................................................................................. 266
Identification Register......................................................................................................................... 266
14.
15.
16.
PIN CONFIGURATION...................................................................................................271
PACKAGE INFORMATION ............................................................................................272
256-B
ALL
TE-CSBGA (56-G6028-001) ...................................................................................272
15.1
DOCUMENT REVISION HISTORY ................................................................................273
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DS26524 Quad T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 6-1. Block Diagram ......................................................................................................................................... 17
Figure 6-2. Detailed Block Diagram........................................................................................................................... 18
Figure 8-1. Backplane Clock Generation................................................................................................................... 27
Figure 8-2. Device Interrupt Information Flow Diagram............................................................................................. 30
Figure 8-3. IBO Multiplexer Equivalent Circuit—4.096MHz ...................................................................................... 35
Figure 8-4. IBO Multiplexer Equivalent Circuit—8.192MHz ...................................................................................... 36
Figure 8-5. IBO Multiplexer Equivalent Circuit—16.384MHz .................................................................................... 37
Figure 8-6. RSYNC Input in H.100 (CT Bus) Mode................................................................................................... 40
Figure 8-7. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode ....................................................................... 41
Figure 8-8. CRC-4 Recalculate Method .................................................................................................................... 62
Figure 8-9. Receive HDLC Example.......................................................................................................................... 68
Figure 8-10. HDLC Message Transmit Example....................................................................................................... 70
Figure 8-11. Network Connection for Software-Selected Termination—Longitudinal Protection ............................. 72
Figure 8-12. T1/J1 Transmit Pulse Templates .......................................................................................................... 76
Figure 8-13. E1 Transmit Pulse Templates ............................................................................................................... 77
Figure 8-14. Typical Monitor Application ................................................................................................................... 79
Figure 8-15. Jitter Attenuation ................................................................................................................................... 81
Figure 8-16. Analog Loopback................................................................................................................................... 82
Figure 8-17. Local Loopback ..................................................................................................................................... 82
Figure 8-18. Remote Loopback ................................................................................................................................. 83
Figure 8-19. Dual Loopback ...................................................................................................................................... 83
Figure 9-1. Register Memory Map for the DS26524.................................................................................................. 87
Figure 10-1. T1 Receive-Side D4 Timing ................................................................................................................ 233
Figure 10-2. T1 Receive-Side ESF Timing.............................................................................................................. 233
Figure 10-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 234
Figure 10-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 234
Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 235
Figure 10-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode.................................................................. 236
Figure 10-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode .............................................................. 237
Figure 10-8. T1 Transmit-Side D4 Timing ............................................................................................................... 238
Figure 10-9. T1 Transmit-Side ESF Timing............................................................................................................. 238
Figure 10-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 239
Figure 10-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 239
Figure 10-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 240
Figure 10-13. T1 Transmit-Side Interleave Bus Operation—BYTE Mode............................................................... 241
Figure 10-14. T1 Transmit Interleave Bus Operation—FRAME Mode.................................................................... 242
Figure 10-15. E1 Receive-Side Timing.................................................................................................................... 243
Figure 10-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 243
Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 244
Figure 10-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 244
Figure 10-19. E1 Transmit-Side Timing................................................................................................................... 245
Figure 10-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ........................................................... 245
Figure 10-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 246
Figure 10-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 246
Figure 10-23. E1 G.802 Timing ............................................................................................................................... 247
Figure 12-1. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 251
Figure 12-2. Intel Bus Write Timing (BTS = 0)......................................................................................................... 251
Figure 12-3. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 252
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