ATmega256/128/64RFR2
Features
•
•
•
•
Network support by hardware assisted Multiple PAN Address Filtering
Advanced Hardware assisted Reduced Power Consumption
®
High Performance, Low Power AVR 8-Bit Microcontroller
Advanced RISC Architecture
-
135 Powerful Instructions – Most Single Clock Cycle Execution
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32x8 General Purpose Working Registers / On-Chip 2-cycle Multiplier
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Up to 16 MIPS Throughput at 16 MHz and 1.8V – Fully Static Operation
Non-volatile Program and Data Memories
-
256K/128K/64K Bytes of In-System Self-Programmable Flash
•
Endurance: 10’000 Write/Erase Cycles @ 125° (25’000 Cycles @ 85°
C
C)
-
8K/4K/2K Bytes EEPROM
•
Endurance: 20’000 Write/Erase Cycles @ 125° (100’000 Cycles @ 25°
C
C)
-
32K/16K/8K Bytes Internal SRAM
JTAG (IEEE std. 1149.1 compliant) Interface
-
Boundary-scan Capabilities According to the JTAG Standard
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Extensive On-chip Debug Support
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Programming of Flash EEPROM, Fuses and Lock Bits through the JTAG interface
Peripheral Features
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Multiple Timer/Counter & PWM channels
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Real Time Counter with Separate Oscillator
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10-bit, 330 ks/s A/D Converter; Analog Comparator; On-chip Temperature Sensor
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Master/Slave SPI Serial Interface
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Two Programmable Serial USART
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Byte Oriented 2-wire Serial Interface
Advanced Interrupt Handler and Power Save Modes
Watchdog Timer with Separate On-Chip Oscillator
Power-on Reset and Low Current Brown-Out Detector
Fully integrated Low Power Transceiver for 2.4 GHz ISM Band
-
High Power Amplifier support by TX spectrum side lobe suppression
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Supported Data Rates: 250 kb/s and 500 kb/s, 1 Mb/s, 2 Mb/s
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-100 dBm RX Sensitivity; TX Output Power up to 3.5 dBm
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Hardware Assisted MAC (Auto-Acknowledge, Auto-Retry)
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32 Bit IEEE 802.15.4 Symbol Counter
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SFD-Detection, Spreading; De-Spreading; Framing ; CRC-16 Computation
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Antenna Diversity and TX/RX control / TX/RX 128 Byte Frame Buffer
-
Phase measurement support
PLL synthesizer with 5 MHz and 500 kHz channel spacing for 2.4 GHz ISM Band
Hardware Security (AES, True Random Generator)
Integrated Crystal Oscillators (32.768 kHz & 16 MHz, external crystal needed)
I/O and Package
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38 Programmable I/O Lines
-
64-pad QFN (RoHS/Fully Green)
Temperature Range: -40° to 125° Industrial
C
C
Ultra Low Power consumption (1.8 to 3.6V) for AVR & Rx/Tx: 10.1mA/18.6 mA
-
CPU Active Mode (16MHz): 4.1 mA
-
2.4GHz Transceiver: RX_ON 6.0 mA / TX 14.5 mA (maximum TX output power)
-
Deep Sleep Mode: <700nA @ 25°
C
Speed Grade: 0 – 16 MHz @ 1.8 – 3.6V range with integrated voltage regulators
•
•
•
8-bit
Microcontroller
with Low Power
2.4GHz
Transceiver for
ZigBee and
IEEE 802.15.4
ATmega256RFR2
ATmega128RFR2
ATmega64RFR2
•
•
•
•
•
•
•
•
•
•
•
Applications
•
ZigBee / IEEE 802.15.4-2011/2006/2003
™
– Full and Reduced Function Device
•
General Purpose 2.4GHz ISM Band Transceiver with Microcontroller
•
RF4CE, SP100, WirelessHART
™
, ISM Applications and IPv6 / 6LoWPAN
®
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1 Pin Configurations
Figure 1-1.
Pinout ATmega256/128/64RFR2
[PE7:ICP3:INT7:CLKO]
[XTAL1]
[AVDD]
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
[PF2:ADC2:DIG2] 1
[PF3:ADC3:DIG4] 2
[PF4:ADC4:TCK] 3
[PF5:ADC5:TMS] 4
[PF6:ADC6:TDO] 5
[PF7:ADC7:TDI] 6
[AVSS_RFP] 7
[RFP] 8
[RFN] 9
[AVSS_RFN] 10
[TST] 11
[RSTN] 12
[RSTON] 13
[PG0:DIG3] 14
[PG1:DIG1] 15
[PG2:AMR] 16
[PD3:TXD1:INT3]
[PD5:XCK1]
[PD4:ICP1]
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
0
0
[PD0:SCL:INT0]
[PD1:SDA:INT1]
[PD2:RXD1:INT2]
[DVSS:DSVSS]
[PG3:TOSC2]
[PG4:TOSC1]
[PG5:OC0B]
[PD6:T1]
[DEVDD]
[PD7:T0]
[DVDD]
[DVDD]
[DVSS]
Exposed paddle: [AVSS]
Index corner
48 [PE2:XCK0:AIN0]
47 [PE1:TXD0]
46 [PE0:RXD0:PCINT8]
45 [DVSS]
44 [DEVDD]
[PE3:OC3A:AIN1]
43 [PB7:OC0A:OC1C:PCINT7]
42 [PB6:OC1B:PCINT6]
41 [PB5:OC1A:PCINT5]
40 [PB4:OC2A:PCINT4]
39 [PB3:MISO:PDO:PCINT3]
38 [PB2:MOSI:PDI:PCINT2]
37 [PB1:SCK:PCINT1]
36 [PB0:SSN:PCINT0]
35 [DVSS]
34 [DEVDD]
33 [CLKI]
[PE5:OC3C:INT5]
ATmega256/128/64RFR2
Note:
The large center pad underneath the QFN/MLF package is made of metal and internally connected
to AVSS. It should be soldered or glued to the board to ensure good mechanical stability. If the
center pad is left unconnected, the package might loosen from the board. It is not recommended to
use the exposed paddle as a replacement of the regular AVSS pins.
2 Disclaimer
Typical values contained in this datasheet are based on simulation and characterization
results of other AVR microcontrollers and radio transceivers manufactured in a similar
process technology. Minimum and Maximum values will be available after the device is
characterized.
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[PE4:OC3B:INT4]
[AVSS:ASVSS]
[PE6:T3:INT6]
[PF1:ADC1]
[PF0:ADC0]
[DEVDD]
[XTAL2]
[EVDD]
[DVSS]
[AVSS]
[AREF]
ATmega256/128/64RFR2
3 Overview
The ATmega256/128/64RFR2 is a low-power CMOS 8-bit microcontroller based on the
AVR enhanced RISC architecture combined with a high data rate transceiver for the 2.4
GHz ISM band.
By executing powerful instructions in a single clock cycle, the device achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
The radio transceiver provides high data rates from 250 kb/s up to 2 Mb/s, frame
handling, outstanding receiver sensitivity and high transmit output power enabling a
very robust wireless communication.
3.1 Block Diagram
Figure 3-1
Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working
registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU). Two
independent registers can be accessed with one single instruction executed in one
clock cycle. The resulting architecture is very code efficient while achieving throughputs
up to ten times faster than conventional CISC microcontrollers. The system includes
internal voltage regulation and an advanced power management. Distinguished by the
small leakage current it allows an extended operation time from battery.
The radio transceiver is a fully integrated ZigBee solution using a minimum number of
external components. It combines excellent RF performance with low cost, small size
and low current consumption. The radio transceiver includes a crystal stabilized
fractional-N synthesizer, transmitter and receiver, and full Direct Sequence Spread
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Spectrum Signal (DSSS) processing with spreading and despreading. The device is
fully compatible with IEEE802.15.4-2011/2006/2003 and ZigBee standards.
The ATmega256/128/64RFR2 provides the following features: 256K/128K/64K Bytes of
In-System Programmable (ISP) Flash with read-while-write capabilities, 8K/4K/2K Bytes
EEPROM, 32K/16K/8K Bytes SRAM, up to 35 general purpose I/O lines, 32 general
purpose working registers, Real Time Counter (RTC), 6 flexible Timer/Counters with
compare modes and PWM, a 32 bit Timer/Counter, 2 USART, a byte oriented 2-wire
Serial Interface, a 8 channel, 10 bit analog to digital converter (ADC) with an optional
differential input stage with programmable gain, programmable Watchdog Timer with
Internal Oscillator, a SPI serial port, IEEE std. 1149.1 compliant JTAG test interface,
also used for accessing the On-chip Debug system and programming and 6 software
selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and
interrupt system to continue functioning. The Power-down mode saves the register
contents but freezes the Oscillator, disabling all other chip functions until the next
interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to
run, allowing the user to maintain a timer base while the rest of the device is sleeping.
The ADC Noise Reduction mode stops the CPU and all I/O modules except
asynchronous timer and ADC, to minimize switching noise during ADC conversions. In
Standby mode, the RC oscillator is running while the rest of the device is sleeping. This
allows very fast start-up combined with low power consumption. In Extended Standby
mode, both the main RC oscillator and the asynchronous timer continue to run.
Typical supply current of the microcontroller with CPU clock set to 16MHz and the radio
transceiver for the most important states is shown in the
Figure 3-2 below.
Figure 3-2
Radio transceiver and microcontroller (16MHz) supply current
20
1.8V
3.0V
3.6V
I(DEVDD,EVDD) [mA]
15
RPC disabled
18,6mA
16,6mA
10
RPC enabled
□
10.1mA
5
250nA
700nA
Deep Sleep
4,1mA
4,7mA
0
SLEEP
TRX_OFF
RX_ON
BUSY_TX
Radio transceiver and microcontroller (16MHz) supply current
The transmit output power is set to maximum. If the radio transceiver is in SLEEP mode
the current is dissipated by the AVR microcontroller only.
In Deep Sleep mode all major digital blocks with no data retention requirements are
disconnected from main supply providing a very small leakage current. Watchdog timer,
MAC symbol counter and 32.768kHz oscillator can be configured to continue to run.
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ATmega256/128/64RFR2
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
trough an SPI serial interface, by a conventional nonvolatile memory programmer, or by
on on-chip boot program running on the AVR core. The boot program can use any
interface to download the application program in the application Flash memory.
Software in the boot Flash section will continue to run while the application Flash
section is updated, providing true Read-While-Write operation. By combining an 8 bit
RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega256/128/64RFR2 is a powerful microcontroller that provides a highly flexible
and cost effective solution to many embedded control applications.
The ATmega256/128/64RFR2 AVR is supported with a full suite of program and system
development tools including: C compiler, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits.
3.2 Pin Descriptions
3.2.1 EVDD
External analog supply voltage.
3.2.2 DEVDD
External digital supply voltage.
3.2.3 AVDD
Regulated analog supply voltage (internally generated).
3.2.4 DVDD
Regulated digital supply voltage (internally generated).
3.2.5 DVSS
Digital ground.
3.2.6 AVSS
Analog ground.
3.2.7 Port B (PB7...PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also provides
ATmega256/128/64RFR2.
3.2.8 Port D (PD7...PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also provides
ATmega256/128/64RFR2.
3.2.9 Port E (PE7...PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port E output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port E pins that are externally pulled low will source
functions
of
various
special
features
of
the
functions
of
various
special
features
of
the
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