Crystal-to-LVPECL 100MHz Clock
Synthesizer
843S304I-100
Data Sheet
General Description
The 843S304I-100 is a PLL-based clock generator specifically
designed for low phase noise applications. This device generates a
100MHz differential LVPECL clock from a input reference of 25MHz.
The input reference may be derived from an external source or by
the addition of a 25MHz crystal to the on-chip crystal oscillator. An
external reference is applied to the PCLK pins.
The nominal output frequency of 100MHz may be margined by
approximately ±5% by changing the M divider value via the I
2
C
interface.
The device offers spread spectrum clock output for reduced EMI
applications. An I
2
C bus interface is used to enable or disable spread
spectrum operation as well as set the amount of spread. The
843S304I-100 is available in a lead-free 32-Lead VFQFN package.
Features
•
•
•
•
•
•
•
•
•
•
Four LVPECL output pairs
Crystal oscillator interface: 25MHz
Output frequency: 100MHz
PCI Express Gen 2 (5 Gb/s) Jitter compliant
RMS phase jitter @ 100MHz (12kHz – 20MHz): 1.01ps (typical)
I
2
C support with readback capabilities up to 400kHz
Spread Spectrum for electromagnetic interference (EMI) reduction
3.3V operating supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
HiPerClockS™
Block Diagram
nCLK_EN
Pulldown
REF_SEL
Pulldown
PCLK
Pulldown
nPCLK
Pullup/Pulldown
25MHz
Pin Assignment
nQ1
nQ2
V
CC
V
CC
32 31 30 29 28 27 26 25
V
CC
1
4
REF_SEL
Q[1:4]
nQ[1:4]
1
2
24
V
EE
Q1
V
CC
V
EE
Q2
23 nQ3
22
21
Q3
V
CC
PLL
OSC
0
XTAL_IN
Divider
Network
V
EE
3
PCLK 4
nPCLK
V
EE
5
6
4
20 V
EE
19 nQ4
18
17
9
V
CC
XTAL_OUT
V
CCA
7
ADR
Pulldown
SDATA
Pullup
SCLK
Pullup
Q4
V
CC
ADR
SCLK
XTAL_IN
V
CC_XOSC
843S304I-100
32-Lead VFQFN
5.0mm x 5.0mm x 0.925mm
package body
K Package
Top View
©2016 Integrated Device Technology, Inc
1
XTAL_OUT
January 6, 2016
SDATA
V
EE
I
2
C
Logic
nCLK_EN 8
10 11 12 13 14 15 16
843S304I-100 Data Sheet
Table 1. Pin Descriptions
Number
1, 9, 17,
21, 25, 28, 29
2
3, 6,10,
20, 24, 32
4
5
7
8
11
12,
13
14
15
16
18,19
22, 23
26, 27
30, 31
Name
V
CC
REF_SEL
V
EE
PCLK
nPCLK
V
CCA
nCLK_EN
V
CC_XOSC
XTAL_IN,
XTAL_OUT
ADR
SCLK
SDATA
Q4, nQ4
Q3, nQ3
Q2, nQ2
Q1, nQ1
Power
Input
Power
Input
Input
Power
Input
Power
Input
Input
Input
I/O
Output
Output
Output
Output
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Pullup/
Pulldown
Pullup
Type
Description
Core supply pins.
Select input for XTAL (LOW) or PCLK (HIGH).
LVCMOS/LVTTL interface levels.
Negative supply pins.
External 25MHz non-inverted differential reference input. LVPECL input levels.
External 25MHz inverted differential reference input. V
CC
/2 bias voltage when left
floating. LVPECL input levels.
Analog supply for PLL.
Places clock outputs in active state when Low. Places clock outputs in
high-impedance state when High.
Power supply for crystal oscillator. recommended to use RC filter as on V
CCA
.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
I
2
C Address select pin. LVCMOS/LVTTL interface levels.
I
2
C compatible SCLK. This pin has an internal pullup resistor.
LVCMOS/LVTTL interface levels.
I
2
C compatible SDATA. This pin has an internal pullup resistor.
LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
©2016 Integrated Device Technology, Inc
2
January 6, 2016
843S304I-100 Data Sheet
I
2
C Interface - Protocol
The 843S304I-100 uses an I
2
C slave interface for writing
configuration values and reading PLL status bits to and from the
on-chip configuration and status registers. This device uses the
standard I
2
C write format for a write transaction, and a standard I
2
C
combined format for a read transaction.
Figure 1
defines the I
2
C
elements of the standard I
2
C transaction. These elements consist of
SCL
a Start bit, Data bytes, an Acknowledge or Not-Acknowledge bit and
the Stop bit. These elements are arranged to make up the complete
I
2
C transactions as shown in
Figures 2A and 2B.
Figure 2A is a write
transaction while Figure 2B is the combined transaction as used for
the read. Please refer to the
I
2
C Bus Specification
for a detailed
explanation on I
2
C operation.
SDA
START
Valid Data
Acknowledge
STOP
Figure 1. Standard I
2
C Transaction
START (ST)
- defined as high-to-low transition on SDA while holding
SCL HIGH.
DATA
- Between START and STOP cycles, SDA is synchronous with
SCL. Data may change only when SCL is LOW and must be stable
when SCL is HIGH.
ACKNOWLEDGE (AK)
- SDA is driven LOW before the SCL rising
edge and held LOW until the SCL falling edge.
STOP (SP)
- defined as low-to-high transition on SDA while holding
SCL HIGH.
Master-to-Slave
S
DevAdd
W A
RegAdd
A
~RegAdd
A
Data
A P
Slave-to-Master
Figure 2A. Write Transaction
S
DevAdd
W A
RegAdd
A
~RegAdd
A S
DevAdd
R A
Data
A P
Figure 2B. Combined Transaction (Read)
S – Start or Repeated Start
DevAdd
– 7 bit Slave Address
The 843S304I-100 also uses an additional register address byte to
ensure valid I
2
C transactions to the device registers. The byte
contains the 1’s complement of the slave address. This additional
address byte is referred to as the Secure I
2
C interface. This Secure
I
2
C interface can be accessed by most software driver routines that
handle standard I
2
C transactions.
©2016 Integrated Device Technology, Inc
3
January 6, 2016
843S304I-100 Data Sheet
S
ECURE
I
2
C Interface Communication
I
2
C Write Transaction
I
2
C Read Transaction
An I
2
C communication write transaction to the 843S304I-100 is
initiated by the I
2
C master sending a start bit. A start bit is a
high-to-low transition on the serial data (SDA) input/output line while
the serial clock (SCL) input is high. After the start condition, the 7 bit
I
2
C slave-address is sent, MSB first, followed by the read/~write bit.
The read/~write bit is set low to indicate a write operation. After
receiving the valid I
2
C slave-address, the slave device,
843S304I-100 responds with an acknowledge (ACK). Next, the
master sends the 8 bit register address that is to be accessed by this
transaction. Again the 843S304I-100 responds with an acknowledge
bit. The master then sends the one’s complement of the 8 bit
register address. This device again acknowledges. Next the master
sends the 8 bit data value to be stored in the previously addressed
register. The843S304I-100 will acknowledge and lastly the master
will issue a stop.
A read operation uses the I
2
C Combined Transaction. The combined
transaction has a direction change from a write to a read in the
middle of the transaction, allowing a register address to be sent to
the 843S304I-100 and data to be received from the slave device. As
with a write, the combined transaction starts with the master sending
a start condition and is then followed by the 7 bit slave address, and
then followed by the R/~W bit being set for a write. This slave, if
properly addressed, will respond with an Acknowledge (A). Next, as
with the write transaction, the master sends the 8 bit register
address that is to be accessed by this transaction. Once again this
device would respond with an acknowledge. The master then sends
the one’s complement of the 8 bit register address with an
acknowledgment from the slave. The master will next send a
repeated start bit followed by the slave address and the R/~W bit set
to a one which is for a read operation. The 843S304I-100 will
acknowledge and then proceed to send the data byte associated
with the previously addressed register. The master will acknowledge
and then send a stop bit indicating the end of the transaction.
S
YNTHESIZER
C
ONFIGURATION AND
I
2
C P
ROGRAMMING
R
EGISTERS
The 843S304I-100 uses the Secure I
2
C interface to configure the
internal dividers of the PLL. The Secure I
2
C interface allows the
change of the M dividers, and additionally, may be used to turn on,
select the amount, and select the direction of spread spectrum
modulation through a series of read/write 8 bit registers.
Table 3
shows the registers, their address, and description of each of the
Table 3. Register Table
Register Address
00
01
Description
Command Register
Lower M Dividers
N/A
02
03
04
Upper M Dividers
Spread Spectrum Control
Status Read Only
N/A
N/A
UP
N/A
DN
N/A
SS4
N/A
SS3
N/A
SS2
N/A
SS1
N/A
SS0
N/A
N/A
M10
M9
M8
M7
M6
M5
D7
1
M4
D6
nCL
M3
D5
nST
M2
D4
nCP
M1
D3
0
M0
D2
CL
N/A
D1
ST
N/A
D0
CP
N/A
bits in the registers. Some of the bits in these registers are not
defined and are ignored on writes and will read-back as zeros on an
I
2
C read transaction. Note, the Command register, which will be
described below is a write only register, and an attempted read of
this register will result in a NACK or not-acknowledge being returned
to the I
2
C master.
©2016 Integrated Device Technology, Inc
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January 6, 2016
843S304I-100 Data Sheet
The 843S304I-100 can be set to decode on of two device I
2
C slave
addresses to minimize the chance of address conflicts on the I
2
C
bus. The specific address that is decoded by the 843S304I-100 is
Table 4. I
2
C Slave Address Table
Bit
ADR = 0 (default)
ADR = 1
A7
1
1
A6
0
0
A5
1
1
A4
1
1
controlled by the setting of the ADR input (pin 14). This input pin
determines the value of the I
2
C address bit A1. See
Table 4
for the
slave addresses for the 843S304I-100.
A3
0
0
A2
0
0
A1
0
1
A0
R/W
R/W
Writing to and Reading from the Secure I
2
C Interface
Data is communicated to and from the 843S304I-100 registers using
the secure I
2
C interface. The data is read from or written to a
command register and a staging register as shown in
Figure 3.
This
diagram shows the relative location of the Command Register, the
Staging Register and the Main Register. The main register directly
controls the actual PLL operation whose contents is only available
through the Staging and Command registers.
The 8 bit command register (address 00) consists of three command
bits in the lower nibble and the 1’s compliment of those three
command bits in the upper nibble. The setting of one of the bits in
the lower nibble and the clearing of the 1’s complement bit in the
upper nibble is used to command either a copy from the Main
Register to the Staging register, or a Store from the Staging register
to the Main Register, or a Clear of an error flag or flags. All I
2
C writes
to the command register must contain the bitwise compliment of the
three lower bits in the three upper bits or the write will be ignored
and a NACK will be returned from the 843S304I-100. For example
the valid command for the Copy is 1110 0001.
To read the contents of the main register, a command should be sent
to copy the contents of the Main register to the Staging register. This
command is sent by setting bit D0 (CP) and clearing bit D4 (nCP)
with an I
2
C write of 1110 0001 into the command register (register
00). After this command is sent, the contents of the main register is
copied from the Main register to the Staging register and then the
resultant data can be read out by the secure I
2
C interface without
affecting the operation of the synthesizer. The data is read by an I
2
C
read transaction to register 01, register 02, register 03 or register 04.
A multi-byte read may be performed by using the I
2
C specified
register address as the starting address for a multi-byte read
transaction.
In order to store data to the Main register, the data must first be
written to the Staging register associated with the desired register
address. Following the I
2
C write into the Staging register, the data
can be verified, if desired, by reading back the Staging register with
an I C read transaction. The contents in the Staging register can
then be stored into the Main register with a Store command. The
Store command is sent by setting bit D1 (ST) and clearing bit D5
(nST) with an I
2
C write of 1101 0010 into register 00 or the command
register. After this command is sent, the contents of the staging
register is then stored into the main register, allowing a change in
the operation of the synthesizer. A multibyte write to the staging
registers may be done with a multibyte I
2
C write transaction. The
register address and 1’s complement of the register address used in
the I
2
C transaction will represent the beginning address for the write.
The 843S304I-100 will automatically increment the register address
such that the multiple bytes are stored in successive register
locations.
2
Main Register
Copy
Store
I
2
C
SCL
SDA
Command
Register
Staging Register
Figure 3. Writing to and Reading from the Secure I
2
C Interface
©2016 Integrated Device Technology, Inc
5
January 6, 2016
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