Differential-to-LVDS Buffer/Divider
w/Internal Termination
8S89876I
Datasheet
Description
The 8S89876I is a high speed Differential-to-LVDS Buffer/Divider
w/Internal Termination. The 8S89876I has a selectable ÷1, ÷2, ÷4,
÷8, ÷16 output divider. The clock input has internal termination
resistors, allowing it to interface with several differential signal types
while minimizing the number of required external components.
The device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
Features
•
•
•
•
•
•
•
•
•
•
•
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Two LVDS outputs
Frequency divide select options: ÷1, ÷2, ÷4, ÷8, ÷16
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
Input Frequency: 2.5GHz (maximum)
Additive phase jitter, RMS: 0.07ps (typical)
Output skew: 25ps (maximum)
Part-to-part skew: 280ps (maximum)
Propagation Delay: 1.1ns (maximum)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin compatible with the obsolete device 889876AK
Block Diagram
S2
Pullup
Pin Assignment
16 15 14 13
12 IN
11 V
T
10 V
REF_AC
9 nIN
5
6
nc
V
DD
GND
S0
S1
Q0 1
nRESET/
nDISABLE
Pullup
nQ0
Enable
FF
2
Q1 3
nQ1 4
7
V
DD
8
nRESET/
nDISABLE
V
REF_AC
Enable
MUX
Q0
MUX
nQ0
8S89876I
16-Lead VFQFN
3mm x 3mm x 0.9mm package body
K Package
Top View
IN
50Ω
V
T
50Ω
÷2, ÷4,
÷8, ÷16
Q1
nQ1
nIN
S1
Pullup
Decoder
S0
Pullup
©2018 Integrated Device Technology, Inc
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8S89876I Datasheet
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 15, 16
6
7, 14
8
9
10
11
12
13
Name
Q0, nQ0
Q1, nQ1
S2, S1, S0
nc
V
DD
nRESET/
nDISABLE
nIN
V
REF_AC
V
T
IN
GND
Type
Output
Output
Input
Unused
Power
Input
Input
Output
Input
Input
Power
Pullup
Pullup
Description
Differential output pair. Divide by 1, 2, 4, 8, or 16. Unused output pairs must be
terminated with 100
across the differential pair. LVDS interface levels.
Differential output pair. Divide by 1, 2, 4, 8, or 16. Unused output pairs must be
terminated with 100
across the differential pair. LVDS interface levels.
Select pins. Internal 25k
pullup resistor. Logic HIGH if left disconnected (÷16 mode).
Input threshold is V
DD
/2. LVCMOS/LVTTL interface levels.
No connect.
Power supply pins.
When LOW, resets the divider (÷2, ÷4, ÷8 or ÷16 mode). When HIGH, outputs are
active. LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. R
T
= 50
termination to V
T
.
Reference voltage for AC-coupled applications. Equal to V
DD
– 1.35V (approx.).
Maximum sink/source current is 2mA.
Termination center-tap input. Leave pin floating.
Non-inverting LVPECL differential clock input. R
T
= 50
termination to V
T
.
Power supply ground.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37.5
Maximum
Units
k
©2018 Integrated Device Technology, Inc
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8S89876I Datasheet
Function Tables
Table 3A. Control Input Function Table
Input
nRESET/nDISABLE
0
1(default)
Q0, Q1
Disabled; LOW
Enabled
Outputs
nQ0, nQ1
Disabled; HIGH
Enabled
V
DD
/2
nRESET
IN
nIN
V
IN
Swing
nQx
Qx
V
OUT
Swing
t
PD
t
RR
Figure 1. nRESET Timing Diagram
Table 3B. Truth Table
Inputs
nRESET/nDISABLE
1
1
1
1
1
0
S2
0
1
1
1
1
X
S1
X
0
0
1
1
X
S0
X
0
1
0
1
X
Outputs
Q0, nQ0, Q1, nQ1
Reference Clock (pass through)
Reference Clock ÷2
Reference Clock ÷4
Reference Clock ÷8
Reference Clock ÷16 (default)
Qx = LOW, nQx = HIGH; Clock disabled
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8S89876I Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Rating
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
±50mA
±100mA
± 2mA
-40°C to +85°C
74.7C/W (0 mps)
-65C to 150C
Outputs, I
OUT
(NOTE)
Continuos Current
Surge Current
Input Current, IN, nIN
V
T
Current, I
VT
Input Sink/Source, I
REF_AC
Operating Temperature Range, T
A
Package Thermal Impedance,
JA
, (Junction-to-Ambient)
Storage Temperature, T
STG
NOTE: I
OUT
refers to output current supplied by the IDT device only.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
I
IN
V
REF_AC
Parameter
Power Supply Voltage
Power Supply Current
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing; NOTE 1
Differential Input Voltage Swing
Input Current; NOTE 2
Bias Voltage
(IN, nIN)
V
DD
- 1.45
V
DD
– 1.35
(IN, nIN)
(IN, nIN)
(IN, nIN)
80
1.2
0
0.15
0.3
45
V
DD
- 1.25
100
Test Conditions
Minimum
2.97
Typical
3.3
Maximum
3.63
72
120
V
DD
+ 0.3
V
DD
- 0.15
1.8
Units
V
mA
V
V
V
V
mA
V
NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing Diagram
NOTE 2: Guaranteed by design.
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8S89876I Datasheet
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
DD
= V
IN
= 3.63V
V
DD
= 3.63V, V
IN
= 0V
Test Conditions
Minimum
2.2
-0.3
-125
Typical
Maximum
V
DD
+ 0.3
0.8
20
-300
Units
V
V
µA
µA
Table 4C. LVDS DC Characteristics,
V
DD
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
V
OUT
V
OH
V
OL
V
OCM
V
OCM
Parameter
Output Voltage Swing
Output High Voltage
Output Low Voltage
Output Common Mode Voltage
Change in Common Mode Voltage
Test Conditions
Minimum
247
1.35
1.1
1.205
Typical
Maximum
454
1.85
1.5
1.475
50
Units
mV
V
V
V
mV
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
f
IN
t
PD
tsk(o)
tsk(pp)
tjit
t
RR
t
R
/ t
F
Parameter
Input Frequency
Propagation Delay;
NOTE 1
IN-to-Q
0.46
Test Conditions
Minimum
Typical
Maximum
2.5
1.1
25
280
622.08MHz, Integration Range:
12kHz - 20MHz
600
40
150
250
0.07
Units
GHz
ns
ps
ps
ps
ps
ps
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Reset Recovery Time
Output Rise/Fall Time
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
All parameters characterized at
1.7GHz
unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
©2018 Integrated Device Technology, Inc
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