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M5LV-512/256-7SAI

Description
CPLD - Complex Programmable Logic Devices PROGRAM HI DENSITY CPLD
Categorysemiconductor    Programmable logic devices   
File Size799KB,42 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Download Datasheet Parametric View All

M5LV-512/256-7SAI Overview

CPLD - Complex Programmable Logic Devices PROGRAM HI DENSITY CPLD

M5LV-512/256-7SAI Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerLattice
Product CategoryCPLD - Complex Programmable Logic Devices
Shipping RestrictionsThis product may require additional documentation to export from the United States.
RoHSN
ProductMACH 5
Number of Macrocells512
Number of Logic Array Blocks - LABs-
Maximum Operating Frequency100 MHz
Propagation Delay - Max7.5 ns
Number of I/Os256 I/O
Operating Supply Voltage3.3 V
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT
Package / CaseBGA-352
PackagingTray
Height1.17 mm
Length35 mm
Memory TypeEEPROM
Width35 mm
Number of Gates20000
Moisture SensitiveYes
Factory Pack Quantity1
Supply Voltage - Max3.6 V
Supply Voltage - Min3 V
Unit Weight0.262650 oz
MACH 5 CPLD Family
Fifth Generation MACH Architecture
FEATURES
High logic densities and I/Os for increased logic integration
— 128 to 512 macrocell densities
— 68 to 256 I/Os
Wide selection of density and I/O combinations to support most application needs
— 6 macrocell density options
— 7 I/O options
— Up to 4 I/O options per macrocell density
— Up to 5 density & I/O options for each package
Performance features to fit system needs
— 5.5 ns t
PD
Commercial, 7.5 ns t
PD
Industrial
— 182 MHz f
CNT
— Four programmable power/speed settings per block
Flexible architecture facilitates logic design
— Multiple levels of switch matrices allow for performance-based routing
— 100% routability and pin-out retention
— Synchronous and asynchronous clocking, including dual-edge clocking
— Asynchronous product- or sum-term set or reset
— 16 to 64 output enables
— Functions of up to 32 product terms
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— IEEE 1149.1 compliant for boundary scan testing
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port
— PCI compliant (-5/-6/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system design
— Bus-Friendly™ Inputs & I/Os
— Individual output slew rate control
— Hot socketing
— Programmable security bit
Advanced E
2
CMOS process provides high performance, cost effective solutions
Select devices have been discontinued.
See Ordering Information section for product status.
Publication#
20446
Amendment/
0
Rev:
J
Issue Date:
April 2002
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