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MAX693ACSE+T

Description
Supervisory Circuits MPU Supervisor
CategoryPower/power management    The power supply circuit   
File Size2MB,17 Pages
ManufacturerMaxim
Websitehttps://www.maximintegrated.com/en.html
Environmental Compliance
Download Datasheet Parametric View All

MAX693ACSE+T Overview

Supervisory Circuits MPU Supervisor

MAX693ACSE+T Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMaxim
Parts packaging codeSOIC
package instructionSOP, SOP16,.25
Contacts16
Reach Compliance Codecompliant
ECCN codeEAR99
Factory Lead Time9 weeks
Is SamacsysN
Other featuresRESET THRESHOLD VOLTAGE IS 4.4V
Adjustable thresholdYES
Analog Integrated Circuits - Other TypesPOWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length9.9 mm
Humidity sensitivity level1
Number of channels1
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
power supply5 V
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply current (Isup)0.1 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)
Nominal supply voltage (Vsup)4.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
Base Number Matches1
MAX691A/MAX693A/
MAX800L/MAX800M
General Description
Microprocessor Supervisory Circuits
The MAX691A/MAX693A/MAX800L/MAX800M micro-
processor (μP) supervisory circuits are pin-compatible
upgrades to the MAX691, MAX693, and MAX695. They
improve performance with 30μA supply current, 200ms
typ reset active delay on power-up, and 6ns chip-enable
propagation delay. Features include write protection
of CMOS RAM or EEPROM, separate watchdog out-
puts, backup-battery switchover, and a
RESET
output
that is valid with V
CC
down to 1V. The MAX691A/
MAX800L have a 4.65V typical reset-threshold voltage,
and the MAX693A/MAX800Ms’ reset threshold is 4.4V
typical. The MAX800L/MAX800M guarantee power-fail
accuracies to ±2%.
Features
● 200ms Power-OK/Reset Timeout Period
● 1μA Standby Current, 30μA Operating Current
● On-Board Gating of Chip-Enable Signals, 10ns max
Delay
● MaxCap
®
or SuperCap Compatible
● Guaranteed
RESET
Assertion to V
CC
= +1V
● Voltage Monitor for Power-Fail or Low-Battery
Warning
● Power-Fail Accuracy Guaranteed to ±2%
(MAX800L/M)
● Available in 16-Pin Narrow SO, Plastic DIP, and
TSSOP Packages
Applications
Ordering Information
PIN-
PACKAGE
MAX691ACUE
-0°C to +70°C 16 TSSOP
MAX691ACSE
-0°C to +70°C 16 Narrow SO
MAX691ACWE
-0°C to +70°C 16 Wide SO
MAX691ACPE
-0°C to +70°C 16 Plastic DIP
MAX691AC/D
-0°C to +70°C
Dice*
MAX691AEUE
-0°C to +70°C 16 TSSOP
MAX691AESE
-40°C to +85°C 16 Narrow SO
MAX691AEWE
-40°C to +85°C 16 Wide SO
MAX691AEPE
-40°C to +85°C 16 Plastic DIP
Ordering Information continued at end of data sheet.
*Dice
are specified at T
A
= +25°C, DC parameters only.
Devices in PDIP, SO, and TSSOP packages are available in
both leaded and lead-free packaging. Specify lead free by add-
ing the + symbol at the end of the part number when ordering.
Lead free not available for CERDIP package.
PART
TEMP RANGE
CMOS RAM
ADDRESS
DECODE
A0-A15
I/O
Computers
Controllers
Intelligent Instruments
Critical μP Power Monitoring
Typical Operating Circuit
+8V
5V
REGULATOR
0.1µF
1N4148
1
0.47F*
3
V
CC
VBATT
5
BATT ON
V
OUT
2
12
CE
OUT
MAX691A
9
MAX693A
CE
IN 13
PFI
MAX800L
MAX800M
4
7
NO
CONNECTION
8
GND
WDI
OSC IN
PFO
OSC SEL
LOW LINE WDO
6
14
*MaxCap
RESET
11
10
15
Pin Configuration
TOP VIEW
VBATT 1
V
OUT
2
V
CC
3
GND 4
BATT ON 5
LOW LINE
6
OSC IN 7
OSC SEL 8
16 RESET
15
RESET
14
WDO
13
CE
IN
12
CE
OUT
11 WDI
10
PFO
9
PFI
µP
NMI
RESET
AUDIBLE
ALARM
MAX691A
MAX693A
MAX800L
MAX800M
SYSTEM STATUS INDICATORS
MaxCap is a registered trademark of Kanthal Globar, Inc.
DIP/SO/TSSOP
19-0094; Rev 13; 11/17

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